component
A6268KLPTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC LED Drivers, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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A6268KLPTR-T
Allegro MicroSystems, LLC · LED Drivers · TSSOP-16-EP
A6268KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Logic input that enables operation and can be used for direct PWM dimming; the chip enters low power sleep mode when it is held low for longer than the disable time tDIS. |
| 2 | FF1 | output | Open-drain current sink fault flag and isolation control output that is active per Table 1, with absolute maximum rating of -0.3 to 50 V, and it can be pulled up to a logic supply or to the source of a PMOS load-isolation FET. |
| 3 | FF2 | output | Open-drain fault flag output that is active per Table 1 and needs an external pull-up to a logic supply, which should not exceed VREG by 300 mV when VREG is not used. |
| 4 | CKOUT | output | Logic output at the oscillator frequency with a phase shift, used to drive succeeding controllers so that switching instants are interleaved. |
| 5 | IREF | input | Voltage input that reduces the LED current sense voltage, with an absolute maximum of -0.3 to 7 V, and when it is pulled below 1 V the LED current is reduced in a single step. |
| 6 | OSC | input | Resistor to ground sets the internal oscillator, or it accepts an external clock; connecting it to VREG or GND gives about 350 kHz, and the absolute maximum rating is -0.3 to 6.5 V. |
| 7 | SN | input | Negative sense amplifier input for the switch current limit sense resistor RSS, with an absolute maximum rating of -0.3 to 5 V. |
| 8 | SP | input | Positive sense amplifier input for the switch current limit sense resistor RSS, with an absolute maximum rating of -0.3 to 5 V. |
| 9 | SG | output | Gate drive output for the external logic-level MOSFET low-side switch that connects the inductor to ground, with an absolute maximum rating of -0.3 to 6.5 V. |
| 10 | GND | power_in | Ground reference connection that should be connected directly to the negative supply. |
| 11 | VREG | passive | Compensation capacitor connection for the internal 5 V regulator, with an absolute maximum rating of -0.3 to 7 V. |
| 12 | VIN | power_in | Main supply to the control circuit, which requires a bypass capacitor between this pin and GND, with an absolute maximum rating of -0.3 to 50 V and an electrical characterization range of 5 to 40 V. |
| 13 | LP | input | Positive load current sense input for the LED current sense resistor RSL, with a rating of -6 to 6 V with respect to LN. |
| 14 | LN | input | Negative load current sense input for the LED current sense resistor RSL, whose voltage also determines whether boost or buck-boost mode is configured, with an absolute maximum rating of -0.3 to 50 V. |
| 15 | LA | input | LED string anode voltage sense input, which uses an external resistor divider scaled to the number of LEDs and has an absolute maximum rating of -0.3 to 50 V. |
| 16 | LF | input | Single-diode forward voltage reference input that sets the reference for shorted-LED detection against LA, with a rating of -6 to 6 V with respect to LA. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-16-EP |
| Category | Display Modules / LED Drivers / Display Drivers |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage | VIN | -0.3 | 50 | V | 2 | ||
| Pins FF1, EN | -0.3 | 50 | V | 2 | |||
| Pins FF2, CKOUT | -0.3 | 6.5 | V | 2 | |||
| Pin OSC | -0.3 | 6.5 | V | 2 | |||
| Pin SG | -0.3 | 6.5 | V | 2 | |||
| Pins LA, LN | -0.3 | 50 | V | 2 | |||
| Pin LF | -6 | 6 | V | With respect to LA | 2 | ||
| Pin LP | -6 | 6 | V | With respect to LN | 2 | ||
| Pins SP, SN | -0.3 | 5 | V | 2 | |||
| Pin VREG | -0.3 | 7 | V | 2 | |||
| Pin IREF | -0.3 | 7 | V | 2 | |||
| Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature Range | Tstg | -55 | 150 | °C | 2 | ||
| Operating Temperature Range, Range K | TA | -40 | 150 | °C | 2 | ||
| VIN Functional Operating Range | VIN | 5 | 50 | V | 5 | ||
| VIN Quiescent Current | IINQ | 8 | mA | SG open circuit | 5 | ||
| VIN Quiescent Current | IINS | 4 | 10 | μA | EN = GND | 5 | |
| VREG Output Voltage | VREG | 4.85 | 5 | 5.15 | V | IREG = 0 to 2 mA, VIN ≥ 5.3 V | 5 |
| VREG Output Voltage | VREG | 4.7 | V | IREG = 2 mA, VIN = 5 V | 5 | ||
| VREG Current Limit | VREGCL | 25 | mA | 5 | |||
| Maximum Duty Cycle | D | 80 | 85 | % | tON × fOSC | 5 | |
| Pull-Up On Resistance | RDS(on)UP | 3.5 | Ω | TJ = 150°C, IGHx = -100 mA | 5 | ||
| Pull-Down On Resistance | RDS(on)DN | 1.5 | Ω | TJ = 150°C, IGLx = 100 mA | 5 | ||
| Output Low Voltage | VSGL | 0.1 | V | ISG = 100 μA | 5 | ||
| Fault Output Low Voltage | VOL | 0.4 | V | IOL = 1 mA, fault not asserted | 5 | ||
| Fault Output FF1 Leakage Current | IOH1(lkg) | -1 | 1 | μA | VO = 12 V, fault asserted | 5 | |
| Fault Output FF2 Leakage Current | IOH2(lkg) | -5 | 5 | μA | VO = 5 V, fault asserted | 5 | |
| Input Low Voltage | VIL | 0.8 | V | 5 | |||
| Input High Voltage | VIH | 2 | V | 5 | |||
| Input Hysteresis | VIhys | 120 | 180 | mV | 5 | ||
| Boost Mode Select Voltage | VLNB | 0.8 | V | Defined by VLN | 5 | ||
| Buck-Boost Mode Select Voltage | VLNBB | 3.5 | V | Defined by VLN | 5 | ||
| Oscillator Frequency | fOSC | 315 | 350 | 385 | kHz | ROSC = 62 kΩ | 6 |
| Minimum Oscillator Frequency | fMIN | 90 | kHz | 6 | |||
| OSC Pin Voltage | VOSC | 1.15 | 1.2 | 1.25 | V | ROSC = 62 kΩ | 6 |
| OSC Input Low Voltage | VOIL | 0.8 | V | 6 | |||
| OSC Input High Voltage | VOIH | 3.5 | V | 6 | |||
| OSC Input Hysteresis | VOihys | 300 | 600 | mV | 6 | ||
| OSC Watchdog Period | tOSWD | 7 | μs | Between successive rising edges | 6 | ||
| CKOUT Output Low Voltage | VCOL | 0.4 | V | IOL = 1 mA | 6 | ||
| Input Common-Mode Range (B mode) | VCMLL | 0 | 1 | V | VLP = VLN | 6 | |
| Current Error | EISL | -5 | 5 | % | 6 | ||
| Switch Current Sense Input Bias Current | IBIASS | -30 | μA | SP = SN = 0 to 2 V | 6 | ||
| Maximum Differential Input Voltage | VIDS | 110 | 150 | 200 | mV | VIDS = VSP, VSN with D = 50% | 6 |
| Input Common-Mode Range | VCMS | 0 | 2 | V | VSP = VSN | 6 | |
| VIN Undervoltage Turn-Off | VINUV | 4.6 | V | Decreasing VIN | 6 | ||
| VIN Undervoltage Hysteresis | VINUVhys | 200 | 400 | mV | 6 | ||
| VREG Undervoltage Turn-Off | VREGUV | 2.9 | 3.65 | 4.4 | V | Decreasing VREG | 6 |
| VREG Undervoltage Hysteresis | VREGUVhys | 170 | 300 | 400 | mV | 6 | |
| LED String Short Voltage | VSCL | 350 | 475 | 600 | mV | 7 | |
| Non-Reference LED Short Offset Voltage | VSCO | 150 | 225 | 300 | mV | 7 | |
| Reference LED Short Offset Voltage | VSCOR | 350 | 475 | 600 | mV | 7 | |
| LED Open Voltage | VOCL | 5 | 5.5 | 6 | V | 7 | |
| Junction to Ambient (4-layer PCB) | RθJA | 34 | °C/W | On 4-layer PCB based on JEDEC standard | 2 | ||
| Junction to Ambient (2-layer PCB) | RθJA | 43 | °C/W | On 2-layer PCB with 3.8 in.2 of copper area each side | 2 | ||
| Junction to Exposed Pad | RθJP | 2 | °C/W | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | thermal pad (suffix LP). It is lead (Pb) free, with 100% matte tin leadframe plating. | 1 |
CAD (KiCad official)
- Symbol:
A6268KLPTR-T - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
a6268klptr-t-etched.step/a6268klptr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a6268klptr-t.step/a6268klptr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (19 pp, sha256
66bee0c3e7530497, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# A6268KLPTR-T
**Allegro MicroSystems, LLC** · LED Drivers · TSSOP-16-EP
A6268KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Logic input that enables operation and can be used for direct PWM dimming; the chip enters low power sleep mode when it is held low for longer than the disable time tDIS. |
| 2 | FF1 | output | Open-drain current sink fault flag and isolation control output that is active per Table 1, with absolute maximum rating of -0.3 to 50 V, and it can be pulled up to a logic supply or to the source of a PMOS load-isolation FET. |
| 3 | FF2 | output | Open-drain fault flag output that is active per Table 1 and needs an external pull-up to a logic supply, which should not exceed VREG by 300 mV when VREG is not used. |
| 4 | CKOUT | output | Logic output at the oscillator frequency with a phase shift, used to drive succeeding controllers so that switching instants are interleaved. |
| 5 | IREF | input | Voltage input that reduces the LED current sense voltage, with an absolute maximum of -0.3 to 7 V, and when it is pulled below 1 V the LED current is reduced in a single step. |
| 6 | OSC | input | Resistor to ground sets the internal oscillator, or it accepts an external clock; connecting it to VREG or GND gives about 350 kHz, and the absolute maximum rating is -0.3 to 6.5 V. |
| 7 | SN | input | Negative sense amplifier input for the switch current limit sense resistor RSS, with an absolute maximum rating of -0.3 to 5 V. |
| 8 | SP | input | Positive sense amplifier input for the switch current limit sense resistor RSS, with an absolute maximum rating of -0.3 to 5 V. |
| 9 | SG | output | Gate drive output for the external logic-level MOSFET low-side switch that connects the inductor to ground, with an absolute maximum rating of -0.3 to 6.5 V. |
| 10 | GND | power_in | Ground reference connection that should be connected directly to the negative supply. |
| 11 | VREG | passive | Compensation capacitor connection for the internal 5 V regulator, with an absolute maximum rating of -0.3 to 7 V. |
| 12 | VIN | power_in | Main supply to the control circuit, which requires a bypass capacitor between this pin and GND, with an absolute maximum rating of -0.3 to 50 V and an electrical characterization range of 5 to 40 V. |
| 13 | LP | input | Positive load current sense input for the LED current sense resistor RSL, with a rating of -6 to 6 V with respect to LN. |
| 14 | LN | input | Negative load current sense input for the LED current sense resistor RSL, whose voltage also determines whether boost or buck-boost mode is configured, with an absolute maximum rating of -0.3 to 50 V. |
| 15 | LA | input | LED string anode voltage sense input, which uses an external resistor divider scaled to the number of LEDs and has an absolute maximum rating of -0.3 to 50 V. |
| 16 | LF | input | Single-diode forward voltage reference input that sets the reference for shorted-LED detection against LA, with a rating of -6 to 6 V with respect to LA. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-16-EP |
| Category | Display Modules / LED Drivers / Display Drivers |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage | VIN | -0.3 | | 50 | V | | 2 |
| Pins FF1, EN | | -0.3 | | 50 | V | | 2 |
| Pins FF2, CKOUT | | -0.3 | | 6.5 | V | | 2 |
| Pin OSC | | -0.3 | | 6.5 | V | | 2 |
| Pin SG | | -0.3 | | 6.5 | V | | 2 |
| Pins LA, LN | | -0.3 | | 50 | V | | 2 |
| Pin LF | | -6 | | 6 | V | With respect to LA | 2 |
| Pin LP | | -6 | | 6 | V | With respect to LN | 2 |
| Pins SP, SN | | -0.3 | | 5 | V | | 2 |
| Pin VREG | | -0.3 | | 7 | V | | 2 |
| Pin IREF | | -0.3 | | 7 | V | | 2 |
| Junction Temperature | TJ(max) | | | 150 | °C | | 2 |
| Storage Temperature Range | Tstg | -55 | | 150 | °C | | 2 |
| Operating Temperature Range, Range K | TA | -40 | | 150 | °C | | 2 |
| VIN Functional Operating Range | VIN | 5 | | 50 | V | | 5 |
| VIN Quiescent Current | IINQ | | | 8 | mA | SG open circuit | 5 |
| VIN Quiescent Current | IINS | | 4 | 10 | μA | EN = GND | 5 |
| VREG Output Voltage | VREG | 4.85 | 5 | 5.15 | V | IREG = 0 to 2 mA, VIN ≥ 5.3 V | 5 |
| VREG Output Voltage | VREG | 4.7 | | | V | IREG = 2 mA, VIN = 5 V | 5 |
| VREG Current Limit | VREGCL | 25 | | | mA | | 5 |
| Maximum Duty Cycle | D | 80 | 85 | | % | tON × fOSC | 5 |
| Pull-Up On Resistance | RDS(on)UP | | | 3.5 | Ω | TJ = 150°C, IGHx = -100 mA | 5 |
| Pull-Down On Resistance | RDS(on)DN | | | 1.5 | Ω | TJ = 150°C, IGLx = 100 mA | 5 |
| Output Low Voltage | VSGL | | | 0.1 | V | ISG = 100 μA | 5 |
| Fault Output Low Voltage | VOL | | | 0.4 | V | IOL = 1 mA, fault not asserted | 5 |
| Fault Output FF1 Leakage Current | IOH1(lkg) | -1 | | 1 | μA | VO = 12 V, fault asserted | 5 |
| Fault Output FF2 Leakage Current | IOH2(lkg) | -5 | | 5 | μA | VO = 5 V, fault asserted | 5 |
| Input Low Voltage | VIL | | | 0.8 | V | | 5 |
| Input High Voltage | VIH | 2 | | | V | | 5 |
| Input Hysteresis | VIhys | 120 | 180 | | mV | | 5 |
| Boost Mode Select Voltage | VLNB | | | 0.8 | V | Defined by VLN | 5 |
| Buck-Boost Mode Select Voltage | VLNBB | 3.5 | | | V | Defined by VLN | 5 |
| Oscillator Frequency | fOSC | 315 | 350 | 385 | kHz | ROSC = 62 kΩ | 6 |
| Minimum Oscillator Frequency | fMIN | 90 | | | kHz | | 6 |
| OSC Pin Voltage | VOSC | 1.15 | 1.2 | 1.25 | V | ROSC = 62 kΩ | 6 |
| OSC Input Low Voltage | VOIL | | | 0.8 | V | | 6 |
| OSC Input High Voltage | VOIH | 3.5 | | | V | | 6 |
| OSC Input Hysteresis | VOihys | 300 | 600 | | mV | | 6 |
| OSC Watchdog Period | tOSWD | 7 | | | μs | Between successive rising edges | 6 |
| CKOUT Output Low Voltage | VCOL | | | 0.4 | V | IOL = 1 mA | 6 |
| Input Common-Mode Range (B mode) | VCMLL | 0 | | 1 | V | VLP = VLN | 6 |
| Current Error | EISL | -5 | | 5 | % | | 6 |
| Switch Current Sense Input Bias Current | IBIASS | -30 | | | μA | SP = SN = 0 to 2 V | 6 |
| Maximum Differential Input Voltage | VIDS | 110 | 150 | 200 | mV | VIDS = VSP, VSN with D = 50% | 6 |
| Input Common-Mode Range | VCMS | 0 | | 2 | V | VSP = VSN | 6 |
| VIN Undervoltage Turn-Off | VINUV | | | 4.6 | V | Decreasing VIN | 6 |
| VIN Undervoltage Hysteresis | VINUVhys | 200 | | 400 | mV | | 6 |
| VREG Undervoltage Turn-Off | VREGUV | 2.9 | 3.65 | 4.4 | V | Decreasing VREG | 6 |
| VREG Undervoltage Hysteresis | VREGUVhys | 170 | 300 | 400 | mV | | 6 |
| LED String Short Voltage | VSCL | 350 | 475 | 600 | mV | | 7 |
| Non-Reference LED Short Offset Voltage | VSCO | 150 | 225 | 300 | mV | | 7 |
| Reference LED Short Offset Voltage | VSCOR | 350 | 475 | 600 | mV | | 7 |
| LED Open Voltage | VOCL | 5 | 5.5 | 6 | V | | 7 |
| Junction to Ambient (4-layer PCB) | RθJA | | 34 | | °C/W | On 4-layer PCB based on JEDEC standard | 2 |
| Junction to Ambient (2-layer PCB) | RθJA | | 43 | | °C/W | On 2-layer PCB with 3.8 in.2 of copper area each side | 2 |
| Junction to Exposed Pad | RθJP | | 2 | | °C/W | | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | thermal pad (suffix LP). It is lead (Pb) free, with 100% matte tin leadframe plating. | 1 |
## CAD (KiCad official)
- Symbol: `A6268KLPTR-T`
- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files: `a6268klptr-t-etched.step` / `a6268klptr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a6268klptr-t.step` / `a6268klptr-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a6268klptr-t-datasheet.pdf) (19 pp, sha256 `66bee0c3e7530497`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/a6268klptr-t-datasheet.pdf)