# A6217KLJTR-T

**Allegro MicroSystems LLC** · LED Drivers · SOIC-8-EP

A6217KLJTR-T from Allegro MicroSystems LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Supply voltage input terminal, rated 6 to 48 V for operation with an absolute maximum of -0.3 to 50 V. |
| 2 | TON | passive | Regulator on-time setting resistor terminal, connected through RON to VIN, which determines the switching frequency. |
| 3 | EN | input | Enable and PWM dimming input, rated up to VIN and logic-level compatible. |
| 4 | CS | input | Drive output current sense feedback; the average CS voltage is regulated at VCSREG (0.2 V typical), with an absolute maximum of -0.3 to 7 V. |
| 5 | VCC | power_out | Internal linear regulator output that requires a 0.1 µF filter capacitor to GND, absolute maximum -0.3 to 7 V, and is not designed to drive an external load. |
| 6 | GND | power_in | Ground terminal. |
| 7 | BOOT | passive | DMOS gate driver bootstrap terminal, with an absolute maximum of -0.3 to VIN + 8 V. |
| 8 | SW | output | Switched output terminal, with an absolute range of -1.5 to VIN + 0.3 V. |
| 9 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-8-EP |
| Category | LED Drivers |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Voltage | VIN | 6 |  | 48 | V |  | 4 |
| Junction Temperature Range (electrical characteristics valid range) | TJ | -40 |  | 125 | °C | Valid at VIN = 12 V; typical values at TJ = 25°C | 4 |
| VIN Pin Shutdown Current | IINSD |  | 1 | 10 | µA | EN shorted to GND | 4 |
| Buck Switch Current Limit Threshold (A6217, 3 A part) | ISWLIM | 3 | 4 | 5 | A |  | 4 |
| Buck Switch On-Resistance | RDS(on) |  | 0.25 | 0.4 | Ω | VBOOT = VIN + 4.3 V, TA = 25°C, ISW = 1 A | 4 |
| BOOT Undervoltage Lockout Threshold | VBOOTUV | 2.7 | 3.5 | 4.3 | V | VBOOT to VSW increasing | 4 |
| Switching Minimum Off-Time | tOFFmin |  | 110 | 150 | ns | VCS = 0 V | 4 |
| Switching Minimum On-Time | tONmin |  | 75 | 100 | ns |  | 4 |
| Selected On-Time | tON | 200 | 250 | 300 | ns | VIN = 12 V, VOUT = 6 V, RON = 31.6 kΩ | 4 |
| Oscillator Frequency Dithering Range | fSW_DITH | -5 |  | 5 | % | RON = 31.6 kΩ; printed as ±5 | 4 |
| Load Current Sense Regulation Threshold | VCSREG | 187.5 | 200 | 210 | mV | VCS decreasing, SW turns on | 4 |
| VCC Regulated Output | VCC | 5.1 | 5.4 | 5.7 | V | 0 mA < ICC < 5 mA, VIN > 6 V | 4 |
| VCC Current Limit | ICCLIM | 5 | 20 |  | mA | VCC = 0 V | 4 |
| Logic High Voltage | VIH | 1.8 |  |  | V | VEN increasing | 4 |
| Logic Low Voltage | VIL |  |  | 0.4 | V | VEN decreasing | 4 |
| Maximum PWM Dimming Off-Time | tPWML | 12 | 20 |  | ms | Measured while EN = low during dimming control, internal references powered on; exceeding tPWML results in shutdown | 4 |
| Input Supply Voltage (absolute maximum) | VIN | -0.3 |  | 50 | V |  | 2 |
| Bootstrap Drive Voltage (absolute maximum) | VBOOT | -0.3 |  |  | V |  | 2 |
| Switching Voltage (absolute maximum) | VSW | -1.5 |  |  | V |  | 2 |
| Linear Regulator Terminal (absolute maximum) | VCC | -0.3 |  | 7 | V | VCC to GND | 2 |
| Enable and TON Voltage (absolute maximum) | VEN, VTON | -0.3 |  |  | V |  | 2 |
| Current Sense Voltage (absolute maximum) | VCS | -0.3 |  | 7 | V |  | 2 |
| Maximum Junction Temperature (absolute maximum) | TJ(max) |  |  | 150 | °C |  | 2 |
| Storage Temperature (absolute maximum) | Tstg | -55 |  | 150 | °C |  | 2 |
| Package Thermal Resistance (Junction to Ambient), SOICN-8 (LJ) | RθJA |  | 35 |  | °C/W | SOICN-8 (LJ) package on 4-layer PCB based on JEDEC standard | 2 |
| Package Thermal Resistance (Junction to Pad) | RθJP |  | 2 |  | °C/W |  | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | are lead (Pb) free, with 100% matte-tin leadframe plating. A6217-DS | 1 |

## CAD (KiCad official)

- Symbol: `A6217KLJTR-T`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `a6217kljtr-t-etched.step` / `a6217kljtr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a6217kljtr-t.step` / `a6217kljtr-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems LLC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586200220456009728) (19 pp, sha256 `066830f6253cdecf`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a6217kljtr-t-datasheet.pdf)