component

A6217KEJTR-1-J

Public Made by Adom

by adom

Allegro MicroSystems, LLC LED Drivers, WDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdisplay modules - led drivers - display driversa6217kejtr-1-jfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
a6217kejtr-1-j / README.md
History Download
Ray Publish 0.1.0 3f2f98c 7d ago

A6217KEJTR-1-J

Allegro MicroSystems, LLC · LED Drivers · WDFN-10-EP(3x3)

A6217KEJTR-1-J from Allegro MicroSystems, LLC, in a WDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Supply voltage input terminal (pins 1 and 2 are tied together), operating range 6 to 48 V, absolute maximum 50 V.
2 VIN power_in Supply voltage input terminal (pins 1 and 2 are tied together), operating range 6 to 48 V, absolute maximum 50 V.
3 TON passive Regulator on-time setting resistor terminal (RON to VIN) that determines the switching frequency of the converter.
4 EN input Input for Enable and PWM dimming, rated up to VIN and logic-level compatible with VIH 1.8 V min and VIL 0.4 V max.
5 CS input Drive output current sense feedback, regulated at 0.2 V typical (VCSREG) across the sense resistor.
6 VCC power_out Internal linear regulator output (5.4 V typical); add a 0.1 µF filter capacitor from this pin to GND, not designed to drive an external load.
7 GND power_in Ground terminal.
8 BOOT passive DMOS gate driver bootstrap terminal, connect a 0.1 µF bootstrap capacitor to SW.
9 SW output Switched output terminal (pins 9 and 10 are tied together) of the buck switch.
10 SW output Switched output terminal (pins 9 and 10 are tied together) of the buck switch.
11 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package WDFN-10-EP(3x3)
Category Display Modules / LED Drivers / Display Drivers
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Supply Voltage VIN 6 48 V VIN = 12 V, TJ = -40°C to 125°C 4
Buck Switch Current Limit Threshold (A6217-1) ISWLIM 1.9 2.2 2.7 A A6217-1 4
Buck Switch On-Resistance RDS(on) 0.25 0.4 Ω VBOOT = VIN + 4.3 V, TA = 25°C, ISW = 1 A 4
BOOT Undervoltage Lockout Threshold VBOOTUV 2.7 3.5 4.3 V VBOOT to VSW increasing 4
Switching Minimum Off-Time tOFFmin 110 150 ns VCS = 0 V 4
Switching Minimum On-Time tONmin 75 100 ns 4
Selected On-Time tON 200 250 300 ns VIN = 12 V, VOUT = 6 V, RON = 31.6 kΩ 4
Load Current Sense Regulation Threshold VCSREG 187.5 200 210 mV VCS decreasing, SW turns on 4
VCC Regulated Output VCC 5.1 5.4 5.7 V 0 mA < ICC < 5 mA, VIN > 6 V 4
VCC Current Limit ICCLIM 5 20 mA VCC = 0 V 4
EN Logic High Voltage VIH 1.8 V VEN increasing 4
EN Logic Low Voltage VIL 0.4 V VEN decreasing 4
Maximum PWM Dimming Off-Time tPWML 12 20 ms Measured while EN = low, during dimming control, and internal references are powered on 4
VIN Pin Shutdown Current IINSD 1 10 µA EN shorted to GND 4
VIN Undervoltage Lockout Threshold VUVLO 5.3 V VIN increasing 4
VIN Undervoltage Lockout Hysteresis VUVLO_HYS 150 mV VIN decreasing 4
VIN Pin Supply Current IIN 2.5 mA VCS = 0.5 V, EN = High 4
VIN Pin Standby Current IINSB 1 mA VCS = 0.5 V, EN = high to low, within 10 ms 4
BOOT Undervoltage Lockout Hysteresis VBOTUVHYS 370 mV VBOOT to VSW decreasing 4
Oscillator Frequency Dithering Range fSW_DITH 5 % RON = 31.6 kΩ, printed ±5 4
Dithering Modulation Frequency fSW_MOD 11 kHz RON = 31.6 kΩ 4
Load Current Sense Bias Current ICSBIAS 0.9 µA VCS = 0.2 V, EN = low 4
EN Pin Pull-Down Resistance RENPD 100 kΩ VEN = 5 V 4
Thermal Shutdown Threshold TSD 165 °C 4
Thermal Shutdown Hysteresis TSDHYS 25 °C 4
Supply Voltage VIN -0.3 50 V 2
Bootstrap Drive Voltage VBOOT -0.3 8 V Upper limit printed as VIN + 8 V 2
Switching Voltage VSW -1.5 0.3 V Upper limit printed as VIN + 0.3 V 2
Linear Regulator Terminal VCC VCC -0.3 7 V VCC to GND 2
Enable and TON Voltage VEN, VTON -0.3 0.3 V Upper limit printed as VIN + 0.3 V 2
Current Sense Voltage VCS -0.3 7 V 2
Maximum Junction Temperature TJ(max) 150 ºC 2
Storage Temperature Tstg -55 150 ºC 2
Package Thermal Resistance (Junction to Ambient) RθJA 45 ºC/W DFN-10 (EJ) package on 4-layer PCB based on JEDEC standard 2
Package Thermal Resistance (Junction to Pad) RθJP 2 ºC/W 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin are lead (Pb) free, with 100% matte-tin leadframe plating. A6217-DS, Rev. 1 1

CAD (KiCad official)

  • Symbol: A6217KEJTR-1-J
  • Footprint: Package_DFN_QFN:WDFN-10-1EP_3x3mm_P0.5mm_EP1.8x2.5mm
  • 3D model: WDFN-10-EP(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: a6217kejtr-1-j-etched.step / a6217kejtr-1-j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a6217kejtr-1-j.step / a6217kejtr-1-j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (19 pp, sha256 3f32829f0b7cf824, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF