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A5984GESTR-T

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Allegro MicroSystems LLC Stepper Motor Driver, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A5984GESTR-T

Allegro MicroSystems LLC · Stepper Motor Driver · QFN-24-EP(4x4)

A5984GESTR-T from Allegro MicroSystems LLC, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT2B output DMOS full-bridge 2 output B; the output drive capacity of the device is up to 40 V and ±2 A.
2 ENABLE input Logic input that disables all FET outputs when high and enables them as required when low, while STEP, DIR and MSx stay active regardless of its state.
3 GND power_in Ground; the GND pins must be tied together externally by connecting to the PAD ground plane under the device.
4 CP1 passive Charge pump capacitor terminal; a 0.1 µF ceramic capacitor (Class 2, ±15% max) is connected between CP1 and CP2.
5 CP2 passive Charge pump capacitor terminal; a 0.1 µF ceramic capacitor (Class 2, ±15% max) is connected between CP1 and CP2.
6 VCP passive Reservoir capacitor terminal; a 0.1 µF ceramic capacitor is required between VCP and VBB to act as a reservoir for the high-side FET gates.
7 nFAULT output Open-drain fault output, active low; it is enabled when an overcurrent event disables the device and latches the outputs off.
8 MS1 input Logic input that sets the microstep resolution together with MS2 and MS3 per Table 1; it has an internal 100 kΩ pull-down and changes take effect at the next STEP rising edge.
9 MS2 input Logic input that sets the microstep resolution together with MS1 and MS3 per Table 1; it has an internal 100 kΩ pull-down and changes take effect at the next STEP rising edge.
10 RESET input Logic input that sets the translator to the Home state and turns off all FET outputs when low; STEP inputs are ignored until RESET is high.
11 ROSC passive Timing set pin: connecting to GND selects APFD with a 16 µs off-time, a resistor to GND sets off-time to ROSC/825 µs, and a pull-up above 3 V selects mixed decay with a 30 µs off-time.
12 SLEEP input Logic input where a logic low puts the device into Sleep mode (current below 10 µA), and 1 ms must elapse after leaving Sleep before a STEP command.
13 MS3 input Logic input that sets the microstep resolution together with MS1 and MS2 per Table 1; it has an internal 100 kΩ pull-down and changes take effect at the next STEP rising edge.
14 STEP input Logic input where each low-to-high transition advances the motor one microstep, with minimum HIGH and LOW pulse widths of 1 µs.
15 REF input Gm reference voltage input with a 0 to 4 V range that sets the maximum current ITripMAX = VREF/(8 × RS).
16 GND power_in Ground; the GND pins must be tied together externally by connecting to the PAD ground plane under the device.
17 DIR input Logic input that sets the direction of motor rotation; changes take effect at the next STEP input rising edge.
18 OUT1B output DMOS full-bridge 1 output B; the output drive capacity of the device is up to 40 V and ±2 A.
19 VBB1 power_in Load supply with an operating range of 8 to 40 V.
20 SENSE1 passive Sense resistor terminal for bridge 1; the SENSE1 pin must not exceed its rated -0.5 to 0.5 V.
21 OUT1A output DMOS full-bridge 1 output A; the output drive capacity of the device is up to 40 V and ±2 A.
22 OUT2A output DMOS full-bridge 2 output A; the output drive capacity of the device is up to 40 V and ±2 A.
23 SENSE2 passive Sense resistor terminal for bridge 2; the SENSE2 pin must not exceed its rated -0.5 to 0.5 V.
24 VBB2 power_in Load supply with an operating range of 8 to 40 V.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems LLC
Package QFN-24-EP(4x4)
Category Motor Driver ICs
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage Range VBB 8 40 V Operating 6
Load Supply Voltage Range VBB 0 40 V During Sleep Mode 6
Output On Resistance RDS(on) 640 860 mΩ Source + Sink Driver, IOUT = -2 A, TA = 25°C 6
Body Diode Forward Voltage (source diode) VF 1.4 V Source Diode, IF = -2 A 6
Body Diode Forward Voltage (sink diode) VF 1.4 V Sink Diode, IF = 2 A 6
Output Driver Slew Rate SROUT 50 100 150 ns 10% to 90% 6
Motor Supply Current IBB 7.5 10 mA fPWM < 50 kHz 6
Motor Supply Current IBB 6.5 8 mA Operating, outputs disabled 6
Motor Supply Current (Sleep Mode) IBB 10 µA Sleep Mode 6
Logic Input Voltage (high) VIN(1) 2 V 6
Logic Input Voltage (low) VIN(0) 0.8 V 6
Logic Input Voltage (sleep) VIN(SLEEP) 0.4 V 6
Logic Input Current (high) IIN(1) -20 20 µA 6
Logic Input Current (low) IIN(0) -20 20 µA 6
Logic Input Hysteresis VHYS(IN) 200 550 mV 6
Blank Time tBLANK 0.7 1 1.3 µs 6
Fixed Off-Time tOFF 20 30 40 µs ROSC = 5 V 6
Fixed Off-Time tOFF 13 16 19 µs ROSC = GND 6
Fixed Off-Time tOFF 23 30 37 µs ROSC = 25 kΩ 6
Reference Input Voltage Range VREF 0 4 V 6
Reference Input Current IREF -3 0 3 µA 6
Current Trip-Level Error errI -15 15 % VREF = 2 V, %ITripMAX = 38.27% 6
Current Trip-Level Error errI -5 5 % VREF = 2 V, %ITripMAX = 70.71% 6
Crossover Dead Time tDT 100 475 800 ns 6
Fault Output Voltage VRST 0.5 V nFAULT pin, IOUT = 1 mA 6
Fault Output Leakage Current ILK 1 µA nFAULT pin, no fault, pull-up to 5 V 6
Overcurrent Protection Threshold IOCPST 2.6 A 6
VBB UVLO Threshold VBBUVLO 6.3 6.85 V VBB rising 6
Load Supply Voltage (absolute maximum) VBB 40 V 2
Output Current IOUT -2 2 A 2
Logic Input Voltage (absolute maximum) VIN -0.3 6 V 2
Motor Outputs Voltage V -2 V Maximum printed as VBB + 2 V 2
Sense Voltage VSENSE -0.5 0.5 V 2
Reference Voltage VREF 5.5 V 2
Operating Ambient Temperature (Range G) TA -40 105 °C Range G 2
Maximum Junction Temperature TJ(max) 150 °C 2
Storage Temperature Tstg -55 150 °C 2
Package Thermal Resistance (ES package) RθJA 37 °C/W ES package; estimated, on 4-layer PCB, based on JEDEC standard; still air 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin for enhanced thermal dissipation and are lead (Pb) free (suffix -T), with 100% matte-tin-plated leadframes. 2

CAD (KiCad official)

  • Symbol: A5984GESTR-T
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: a5984gestr-t-etched.step / a5984gestr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a5984gestr-t.step / a5984gestr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems LLC datasheet (28 pp, sha256 e934c6cbe1bf6530, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF