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A5977GLPTR-T

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Allegro MicroSystems, LLC Motor Driver ICs, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A5977GLPTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · HTSSOP-28

A5977GLPTR-T from Allegro MicroSystems, LLC, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENSE1 passive Sense resistor connection for bridge 1; SENSE voltage must not exceed 0.5 V.
2 HOMEn output Logic output that is low when the translator is in the home state and high otherwise.
3 DIR input Logic input that determines the direction of motor rotation.
4 OUT1A output DMOS full-bridge 1 output A, rated for 40 V and ±2.8 A.
5 PFD input Analog input for mixed-decay setting: above 0.6×VDD gives slow decay, below 0.21×VDD gives fast decay, between gives mixed decay; decouple with 0.1 µF.
6 RC1 passive Analog input for fixed off-time and blanking of bridge 1, set by an external RT and CT to ground.
7 AGND power_in Analog ground; must be connected together with PGND and the thermal pad externally under the device.
8 REF input Gm reference input voltage that sets ITRIPmax = VREF/(8×RS), range 0 to VDD.
9 RC2 passive Analog input for fixed off-time and blanking of bridge 2, set by an external RT and CT to ground.
10 VDD power_in Logic supply voltage, 3 to 5.5 V operating range.
11 OUT2A output DMOS full-bridge 2 output A, rated for 40 V and ±2.8 A.
12 MS2 input Logic input that with MS1 selects the microstep resolution (full to eighth step).
13 MS1 input Logic input that with MS2 selects the microstep resolution (full to eighth step).
14 SENSE2 passive Sense resistor connection for bridge 2; SENSE voltage must not exceed 0.5 V.
15 VBB2 power_in Load supply for bridge 2, 8 to 40 V operating.
16 SR input Logic input where low enables synchronous rectification and high disables it.
17 RESETn input Active-low input that sets the translator to the home state and turns off all DMOS outputs.
18 OUT2B output DMOS full-bridge 2 output B, rated for 40 V and ±2.8 A.
19 STEP input Logic input where each low-to-high transition advances the motor one increment.
20 VREG passive Internally generated regulator for sink-side gate drive; decouple with 0.22 µF to ground.
21 PGND power_in Power ground; must be connected together with AGND and the thermal pad externally under the device.
22 VCP passive Charge pump reservoir capacitor; 0.22 µF ceramic required between VCP and VBB.
23 CP1 passive Charge pump capacitor terminal; 0.22 µF ceramic required between CP1 and CP2.
24 CP2 passive Charge pump capacitor terminal; 0.22 µF ceramic required between CP1 and CP2.
25 OUT1B output DMOS full-bridge 1 output B, rated for 40 V and ±2.8 A.
26 ENABLEn input Active-low input that enables all DMOS outputs; outputs are disabled when high.
27 SLEEPn input Active-low input for minimum power sleep mode; a rising edge resets the translator to home and 1 ms is needed before STEP.
28 VBB1 power_in Load supply for bridge 1, 8 to 40 V operating.
29 PAD power_in Exposed thermal pad (required); must be connected together with AGND and PGND externally under the device.

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package HTSSOP-28
Category Power Management ICs
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage Range (Operating) VBB 8 40 V Operating 5
Load Supply Voltage Range (Sleep) VBB 0 40 V During sleep mode 5
Output Leakage Current IDSS 20 µA VOUT = VBB 5
Output Leakage Current IDSS -20 µA VOUT = 0 V 5
Output On-Resistance Source RDS(On) 0.22 0.3 Ω Source driver, IOUT = -2.5 A, TJ = 25°C 5
Output On-Resistance Sink RDS(On) 0.15 0.24 Ω Sink driver, IOUT = 2.5 A, TJ = 25°C 5
Body Diode Forward Voltage Source VF 1 1.4 V Source diode, IF = -2.5 A 5
Body Diode Forward Voltage VF 1 1.4 V Source diode, IF = 2.5 A 5
VBB Supply Current IBB 8 mA fPWM < 50 kHz, duty cycle = 50% 5
VBB Supply Current IBB 6 mA Operating, outputs disabled 5
VBB Supply Current IBB 1 20 µA Sleep mode (typ printed <1) 5
VDD Supply Current IDD 12 mA fPWM < 50 kHz, duty cycle = 50% 5
VDD Supply Current IDD 10 mA Operating, outputs disabled 5
VDD Supply Current IDD 1 20 µA Sleep mode (typ printed <1) 5
Logic Supply Voltage Range VDD 3 5.5 V Operating 5
Logic Input Voltage high VIN(1) 0.7 V min is 0.7×VDD 5
Logic Input Voltage low VIN(0) 0.3 V max is 0.3×VDD 5
Logic Input Current high IIN(1) -20 1 20 µA VIN = 0.7×VDD (typ printed <1) 5
Logic Input Current low IIN(0) -20 1 20 µA VIN = 0.3×VDD (typ printed <1) 5
Maximum Step Frequency fSTEP 500 kHz 5
HOMEn Output Voltage high VOH 0.7 V IOH = -200 µA; min is 0.7×VDD 5
HOMEn Output Voltage low VOL 0.3 V IOL = 200 µA; max is 0.3×VDD 5
Blank Time tBLANK 700 950 1200 ns RT = 56 kΩ, CT = 680 pF 5
Fixed Off-Time tOFF 30 38 46 µs RT = 56 kΩ, CT = 680 pF 5
Reference Input Voltage Range VREFx 0 V Operating; max is VDD 5
Reference Input Current IREF -3 3 µA 5
Gain Error EG -5 5 % VREF = 2 V, phase current = 100.0% 5
Gain Error EG -10 10 % VREF = 2 V, phase current = 38.3% 5
Crossover Dead Time tDT 100 475 800 ns 5
Motor Output Slew Time tSR 20 120 ns 10% to 90% rising; 90% to 10% falling 5
VDD UVLO Threshold VUV(VBB) 2.45 2.7 2.95 V VBB rising 6
VDD UVLO Hysteresis VUV(VBB)HYS 50 100 mV 6
Overcurrent Protection Threshold IOCPST 3.5 A 6
Thermal Shutdown Temperature TJSD 155 165 175 °C 6
Load Supply Voltage VBB 40 V 2
Logic Supply Voltage VDD 7 V 2
Logic Input Voltage Range VIN -0.3 V Pulsed, tW > 30 ns; max VDD + 0.3 V 2
Logic Input Voltage Range VIN -1 V Pulsed, tW < 30 ns; max VDD + 1 V 2
SENSEx Voltage (DC) VSENSE 0.5 V 2
Output Current IOUT -2.8 2.8 A Do not exceed junction temperature of 150°C 2
Operating Ambient Temperature TA -40 105 °C Range G 2
Junction Temperature TJ(max) 150 °C 2
Storage Temperature Tstg -55 150 °C 2
Package Thermal Resistance RθJA 28 ºC/W Package LP, on 4-layer PCB based on JEDEC standard 2
Thermal Shutdown Hysteresis TJSDHYS 15 °C 6
Overcurrent Latch-Off Time tLATCHOFF(OC) 1.6 ms 6
Overcurrent Protection Blank Time tBLANK(OC) 1.5 µs 6
STEP Minimum high pulse width tA 1 µs 7
STEP Minimum low pulse width tB 1 µs 7
Setup time, input change to STEP tC 200 ns 7
Hold time, input change to STEP tD 200 ns 7
Maximum wakeup time tWU 1 ms 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin with an exposed thermal pad (suffix LP). The package is lead (Pb) free (suffix -T), with 100% matte-tin leadframe plating. 1

CAD (KiCad official)

  • Symbol: A5977GLPTR-T
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28 (KiCad packages3D, STEP)
  • 3D model files: a5977glptr-t-etched.step / a5977glptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a5977glptr-t.step / a5977glptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (16 pp, sha256 37ec9fde01dc585e, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF