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A4992KLPTR-T

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Allegro MicroSystems, LLC Motor Driver ICs, TSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A4992KLPTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · TSSOP-20-EP

A4992KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENSA input Phase A current sense; connect the sense resistor between SENSA and PGND, with SENSA rated -0.3 to 1 V with respect to PGND.
2 OAP output Motor connection for phase A, positive terminal; positive phase current flows from OAM to OAP.
3 RESETn input Resets faults when pulsed low and forces low-power sleep mode when held low longer than tRSD; can be pulled to VBB through 38 kΩ.
4 DIR input Direction logic input with internal pull-down; in serial mode it is the SDI serial data input accepting a 16-bit MSB-first word.
5 REF input Reference input that sets the absolute maximum current level for both phases; it defaults to the internal reference when driven above 2.5 V.
6 AGND power_in Analog reference ground and quiet return for measurement and input references; connect to PGND.
7 MS input Microstep resolution select input with internal pull-down; in serial mode it is the SCK serial clock and must be held high when STEP changes.
8 OBP output Motor connection for phase B, positive terminal; positive phase current flows from OBM to OBP.
9 PGND power_in Digital and power ground; connect to the supply ground and to AGND.
10 SENSB input Phase B current sense; connect the sense resistor between SENSB and PGND, with SENSB rated -0.3 to 1 V with respect to PGND.
11 VBB power_in Main motor supply and chip supply for the internal regulators and charge pump; both VBB pins must be connected together and decoupled to ground.
12 OBM output Motor connection for phase B, negative terminal.
13 VREG power_out Regulated supply for bridge gate drive, decoupled to ground with a 470 nF (10 V) ceramic capacitor.
14 DIAG output Diagnostic open-drain output, active low, indicating a fault when low; it requires an external pull-up resistor.
15 STEP input Step logic input with internal pull-down; the motor advances on the rising edge, and in serial mode it is the active-low STRn serial data strobe.
16 VCP power_out Above-supply voltage for high-side drive; a 100 nF (16 V) ceramic capacitor is connected between VCP and VBB.
17 CP1 passive Charge pump capacitor connection; a 100 nF (50 V) ceramic capacitor is connected between CP1 and CP2.
18 CP2 passive Charge pump capacitor connection; a 100 nF (50 V) ceramic capacitor is connected between CP1 and CP2.
19 OAM output Motor connection for phase A, negative terminal; positive phase current flows from OAM to OAP.
20 VBB power_in Main motor supply and chip supply for the internal regulators and charge pump; both VBB pins must be connected together and decoupled to ground.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package TSSOP-20-EP
Category Power Supply Chip
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range VBB 0 50 V Functional, no unsafe states 6
Supply Voltage Range (outputs driving) VBB 3.8 V Outputs driving 6
Supply Quiescent Current IBBQ 15 mA DIS = 1 6
Supply Quiescent Current IBBQ 1 10 µA RESETn < 0.5 V 6
Internal Regulator Dropout Voltage VREGDO 100 200 mV DIS = 1, RESETn = 1, VBB > 6 V 6
High-Side On-Resistance RDS(on)H 500 600 mΩ VBB = 13.5 V, IOUT = -1 A, TJ = 25°C 6
High-Side On-Resistance RDS(on)H 900 1100 mΩ VBB = 13.5 V, IOUT = -1 A, TJ = 150°C 6
High-Side On-Resistance RDS(on)H 625 750 mΩ VBB = 7 V, IOUT = -1 A, TJ = 25°C 6
High-Side Body Diode Forward Voltage VfH 1.4 V If = 1 A 6
Low-Side On-Resistance RDS(on)L 500 600 mΩ VBB =13.5 V, IOUT = 1 A, TJ = 25°C 6
Low-Side On-Resistance RDS(on)L 900 1100 mΩ VBB = 13.5 V, IOUT = 1 A, TJ = 150°C 6
Low-Side On-Resistance RDS(on)L 625 750 mΩ VBB = 7 V, IOUT = 1 A, TJ = 25°C 6
Low-Side Body Diode Forward Voltage VfL 1.4 V If = -1 A 6
Output Leakage Current IOUT(Lkg) -120 -65 µA DIS = 1, RESETn = 1, VOUT = VBB 6
Output Leakage Current IOUT(Lkg) -200 -120 µA DIS = 1, RESETn = 1, VOUT = 0 V 6
Output Leakage Current IOUT(Lkg) 20 µA DIS = 1, RESETn = 0, VOUT = VBB 6
Output Leakage Current IOUT(Lkg) -20 µA DIS = 1, RESETn = 0, VOUT = 0 V 6
Internal Oscillator Frequency fOSC 3.6 4 4.4 MHz 6
Reference Input Voltage VREF 0.8 2 V 6
Internal Reference Voltage VREFint 1.1 1.2 1.3 V VREF > 2.5 V 6
Current Trip Point Error EITrip -5 5 % VREF = 2 V 6
Input Low Voltage VIL 0.8 V 7
Input Low Voltage for Sleep Mode VILS 0.5 V RESETn input only 7
Input High Voltage VIH 2 V 7
Input Hysteresis VIHys 100 300 mV 7
Output Low Voltage VOL 0.4 V IOL = 2 mA 7
Reset Pulse Width tRST 1 6 µs 7
Reset Shutdown Pulse Width tRSD 40 µs 7
STEP High tSTPL 1 µs 7
STEP Low tSTPH 1 µs 7
Setup Time tSU 200 ns MS, DIR; from control input change to STEP change 7
Hold Time tH 200 ns MS, DIR; from STEP change to control input change 7
Wake-Up from Reset tEN 1 ms 7
Data In Hold Time from Clock Rising tSDIH 10 ns Reference G 7
Strobe High Time tSTRH 1100 ns Reference E 7
Sequence Minimum Hold Time tSSH 58 64.5 72 µs Reference H 7
Serial Mode Exit Time tSSEX 2 µs Reference J 7
Serial Mode Acknowledge Time tSAT 59 65.5 73 µs Reference K 7
Serial Mode Acknowledge Pulse tSAP 921 1024 1127 µs Reference L; consistent fault status 7
VBB Overvoltage Threshold VBBOV 32 34 36 V VBB rising 8
VBB Undervoltage Threshold VBBUV 5.2 5.5 5.8 V VBB falling 8
VBB Undervoltage Hysteresis VBBUVHys 500 760 mV 8
VBB Power-On Reset Threshold VBBPOR 2.8 3 V VBB falling 8
VBB Power-On Reset Hysteresis VBBPORHys 50 100 mV 8
VREG Undervoltage Threshold, High VREGUVH 4.6 4.8 4.95 V VREG falling 8
VREG Undervoltage Hysteresis-High VREGUVHHys 250 370 mV 8
VREG Undervoltage Threshold, Low VREGUVL 3.2 3.35 3.5 V VREG falling 8
VREG Undervoltage Hysteresis, Low VREGUVLHys 100 230 mV 8
High-Side Overcurrent Threshold IOCH 1.4 2.05 2.65 A Sampled after tSCT 8
High-Side Current Limit ILIMH 3 5.5 8 A Active during tSCT 8
Low-Side Overcurrent Sense Voltage VOCL 210 250 290 mV Sampled after tSCT 8
Overcurrent Fault Delay tSCT 1500 2000 2700 ns Default fault delay 8
Open Load Current Threshold Error EIOC -10 10 % VREF = 2 V 8
Hot Temperature Warning Threshold TJWH 125 135 145 °C Temperature increasing 8
Overtemperature Shutdown TJF 155 170 °C Temperature increasing 8
Load Supply Voltage VBB -0.3 50 V with respect to PGND 2
Ambient Operating Temperature Range TA -40 150 °C Limited by power dissipation 2
Maximum Continuous Junction Temperature TJ(max) 150 °C 2
Storage Temperature Range Tstg -55 150 °C 2
Package Thermal Resistance RθJA 29 °C/W Estimated, on 4-layer PCB based on JEDEC standard 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin lead (Pb) free with 100% matte-tin lead frame plating. A4992-DS, Rev. 3 1

CAD (KiCad official)

  • Symbol: A4992KLPTR-T
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: TSSOP-20-EP (KiCad packages3D, STEP)
  • 3D model files: a4992klptr-t-etched.step / a4992klptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4992klptr-t.step / a4992klptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (29 pp, sha256 16cbf88bc32f0574, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF