component
A4986SESTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC New Arrivals, QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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A4986SESTR-T
Allegro MicroSystems, LLC · New Arrivals · QFN-24(4x4)
A4986SESTR-T from Allegro MicroSystems, LLC, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT2B | output | DMOS full-bridge 2 output B, rated up to 35 V and ±2 A. |
| 2 | PH2 | input | Logic input setting the phase (current direction) of bridge 2, with logic levels of VDD×0.7 high and VDD×0.3 low. |
| 3 | GND | power_in | Ground; must be tied together externally with the other GND pin by connecting to the PAD ground plane under the device. |
| 4 | CP1 | passive | Charge pump capacitor terminal; connect a 0.1 µF ceramic capacitor between CP1 and CP2. |
| 5 | CP2 | passive | Charge pump capacitor terminal; connect a 0.1 µF ceramic capacitor between CP1 and CP2. |
| 6 | VCP | passive | Reservoir capacitor terminal; a 0.1 µF ceramic capacitor is required between VCP and VBB for the high-side FET gate supply. |
| 7 | VREG | power_out | Regulator decoupling terminal with nominal 7 V output; must be decoupled with a 0.22 µF ceramic capacitor to ground. |
| 8 | IN02 | input | Logic input bit 0 of the bridge 2 current DAC, with an internal pull-down of typically 100 kΩ. |
| 9 | IN12 | input | Logic input bit 1 of the bridge 2 current DAC, with an internal pull-down of typically 50 kΩ. |
| 10 | IN11 | input | Logic input bit 1 of the bridge 1 current DAC (2-bit DAC selects 33%, 66%, 100% of peak current or output disable). |
| 11 | ROSC | input | Timing set for fixed off-time: tie to VDD or ground for 30 µs, or connect a resistor to ground for tOFF ≈ ROSC/825 (µs). |
| 12 | SLEEP | input | Active-low logic input; a logic low puts the device into Sleep mode (< 10 µA), and a 1 ms delay is needed after wake-up before issuing commands. |
| 13 | VDD | power_in | Logic supply, operating range 3.0 to 5.5 V. |
| 14 | IN01 | input | Logic input bit 0 of the bridge 1 current DAC. |
| 15 | REF | input | Gm reference voltage input (VREF 0 to 4 V) setting ITripMAX = VREF/(8×RS). |
| 16 | GND | power_in | Ground; must be tied together externally with the other GND pin by connecting to the PAD ground plane under the device. |
| 17 | PH1 | input | Logic input setting the phase (current direction) of bridge 1. |
| 18 | OUT1B | output | DMOS full-bridge 1 output B, rated up to 35 V and ±2 A. |
| 19 | VBB1 | power_in | Load supply for bridge 1, operating range 8 to 35 V. |
| 20 | SENSE1 | passive | Sense resistor terminal for bridge 1; voltage must not exceed the ±0.5 V maximum rating. |
| 21 | OUT1A | output | DMOS full-bridge 1 output A, rated up to 35 V and ±2 A. |
| 22 | OUT2A | output | DMOS full-bridge 2 output A, rated up to 35 V and ±2 A. |
| 23 | SENSE2 | passive | Sense resistor terminal for bridge 2; voltage must not exceed the ±0.5 V maximum rating. |
| 24 | VBB2 | power_in | Load supply for bridge 2, operating range 8 to 35 V. |
| 25 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | QFN-24(4x4) |
| Category | Others |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage | VBB | 35 | V | 2 | |||
| Output Current | IOUT | -2 | 2 | A | 2 | ||
| Logic Input Voltage | VIN | -0.3 | 5.5 | V | 2 | ||
| Logic Supply Voltage | VDD | -0.3 | 5.5 | V | 2 | ||
| Motor Outputs Voltage | -2 | 37 | V | 2 | |||
| Sense Voltage | VSENSE | -0.5 | 0.5 | V | 2 | ||
| Reference Voltage | VREF | 5.5 | V | 2 | |||
| Operating Ambient Temperature | TA | -20 | 85 | °C | Range S | 2 | |
| Maximum Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature | Tstg | -55 | 150 | °C | 2 | ||
| Load Supply Voltage Range, operating | VBB | 8 | 35 | V | Operating | 4 | |
| Load Supply Voltage Range, sleep | VBB | 0 | 35 | V | During Sleep Mode | 4 | |
| Logic Supply Voltage Range | VDD | 3 | 5.5 | V | Operating | 4 | |
| Source Output On Resistance | RDSON | 320 | 430 | mΩ | Source Driver, IOUT = -1.5 A | 4 | |
| Sink Output On Resistance | RDSON | 320 | 430 | mΩ | Sink Driver, IOUT = 1.5 A | 4 | |
| Source Diode Forward Voltage | VF | 1.3 | V | Source Diode, IF = -1.5 A | 4 | ||
| Sink Diode Forward Voltage | VF | 1.3 | V | Sink Diode, IF = 1.5 A | 4 | ||
| Motor Supply Current | IBB | 4 | mA | fPWM < 50 kHz | 4 | ||
| Motor Supply Current, outputs disabled | IBB | 2 | mA | Operating, outputs disabled | 4 | ||
| Motor Supply Current, sleep | IBB | 10 | μA | Sleep Mode | 4 | ||
| Logic Supply Current | IDD | 8 | mA | fPWM < 50 kHz | 4 | ||
| Logic Supply Current, outputs off | IDD | 5 | mA | Outputs off | 4 | ||
| Logic Supply Current, sleep | IDD | 10 | μA | Sleep Mode | 4 | ||
| Logic Input Voltage high | VIN(1) | 0.7 | x VDD | printed as VDD × 0.7 | 4 | ||
| Logic Input Voltage low | VIN(0) | 0.3 | x VDD | printed as VDD × 0.3 | 4 | ||
| Logic Input Current high | IIN(1) | -20 | 1 | 20 | µA | VIN = VDD × 0.7; typ printed <1.0 | 4 |
| Logic Input Current low | IIN(0) | -20 | 1 | 20 | µA | VIN = VDD × 0.3; typ printed <1.0 | 4 |
| Logic Input Pull-down IN02 | RIN02 | 100 | kΩ | 4 | |||
| Logic Input Pull-down IN12 | RIN12 | 50 | kΩ | 4 | |||
| Logic Input Hysteresis | VHYS(IN) | 5 | 11 | 19 | % | As a % of VDD | 4 |
| Blank Time | tBLANK | 0.7 | 1 | 1.3 | μs | 4 | |
| Fixed Off-Time, OSC tied | tOFF | 20 | 30 | 40 | μs | OSC = VDD or GND | 4 |
| Fixed Off-Time, ROSC | tOFF | 23 | 30 | 37 | μs | ROSC = 25 kΩ | 4 |
| Reference Input Voltage Range | VREF | 0 | 4 | V | 4 | ||
| Reference Input Current | IREF | -3 | 0 | 3 | μA | 4 | |
| Current Trip-Level Error 33.3% | errI | 15 | % | VREF = 2 V, %ITripMAX = 33.3%; printed ±15 | 4 | ||
| Current Trip-Level Error 66.7% | errI | 5 | % | VREF = 2 V, %ITripMAX = 66.7%; printed ±5 | 4 | ||
| Current Trip-Level Error 100% | errI | 5 | % | VREF = 2 V, %ITripMAX = 100.00%; printed ±5 | 4 | ||
| Crossover Dead Time | tDT | 100 | 475 | 800 | ns | 4 | |
| Overcurrent Protection Threshold | IOCPST | 2.1 | A | 4 | |||
| Thermal Shutdown Temperature | TTSD | 165 | °C | 4 | |||
| Thermal Shutdown Hysteresis | TTSDHYS | 15 | °C | 4 | |||
| VDD Undervoltage Lockout | VDDUVLO | 2.7 | 2.8 | 2.9 | V | VDD rising | 4 |
| VDD Undervoltage Hysteresis | VDDUVLOHYS | 90 | mV | 4 | |||
| Package Thermal Resistance (ES) | RθJA | 37 | °C/W | ES package; estimated, on 4-layer PCB, based on JEDEC standard, still air | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | thermal dissipation and are lead (Pb) free (suffix -T), with 100% matte tin plated leadframes. | 1 |
CAD (KiCad official)
- Symbol:
A4986SESTR-T - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
a4986sestr-t-etched.step/a4986sestr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a4986sestr-t.step/a4986sestr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (17 pp, sha256
ff5b906680415f46, retrieved 2026-11-02, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# A4986SESTR-T
**Allegro MicroSystems, LLC** · New Arrivals · QFN-24(4x4)
A4986SESTR-T from Allegro MicroSystems, LLC, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT2B | output | DMOS full-bridge 2 output B, rated up to 35 V and ±2 A. |
| 2 | PH2 | input | Logic input setting the phase (current direction) of bridge 2, with logic levels of VDD×0.7 high and VDD×0.3 low. |
| 3 | GND | power_in | Ground; must be tied together externally with the other GND pin by connecting to the PAD ground plane under the device. |
| 4 | CP1 | passive | Charge pump capacitor terminal; connect a 0.1 µF ceramic capacitor between CP1 and CP2. |
| 5 | CP2 | passive | Charge pump capacitor terminal; connect a 0.1 µF ceramic capacitor between CP1 and CP2. |
| 6 | VCP | passive | Reservoir capacitor terminal; a 0.1 µF ceramic capacitor is required between VCP and VBB for the high-side FET gate supply. |
| 7 | VREG | power_out | Regulator decoupling terminal with nominal 7 V output; must be decoupled with a 0.22 µF ceramic capacitor to ground. |
| 8 | IN02 | input | Logic input bit 0 of the bridge 2 current DAC, with an internal pull-down of typically 100 kΩ. |
| 9 | IN12 | input | Logic input bit 1 of the bridge 2 current DAC, with an internal pull-down of typically 50 kΩ. |
| 10 | IN11 | input | Logic input bit 1 of the bridge 1 current DAC (2-bit DAC selects 33%, 66%, 100% of peak current or output disable). |
| 11 | ROSC | input | Timing set for fixed off-time: tie to VDD or ground for 30 µs, or connect a resistor to ground for tOFF ≈ ROSC/825 (µs). |
| 12 | SLEEP | input | Active-low logic input; a logic low puts the device into Sleep mode (< 10 µA), and a 1 ms delay is needed after wake-up before issuing commands. |
| 13 | VDD | power_in | Logic supply, operating range 3.0 to 5.5 V. |
| 14 | IN01 | input | Logic input bit 0 of the bridge 1 current DAC. |
| 15 | REF | input | Gm reference voltage input (VREF 0 to 4 V) setting ITripMAX = VREF/(8×RS). |
| 16 | GND | power_in | Ground; must be tied together externally with the other GND pin by connecting to the PAD ground plane under the device. |
| 17 | PH1 | input | Logic input setting the phase (current direction) of bridge 1. |
| 18 | OUT1B | output | DMOS full-bridge 1 output B, rated up to 35 V and ±2 A. |
| 19 | VBB1 | power_in | Load supply for bridge 1, operating range 8 to 35 V. |
| 20 | SENSE1 | passive | Sense resistor terminal for bridge 1; voltage must not exceed the ±0.5 V maximum rating. |
| 21 | OUT1A | output | DMOS full-bridge 1 output A, rated up to 35 V and ±2 A. |
| 22 | OUT2A | output | DMOS full-bridge 2 output A, rated up to 35 V and ±2 A. |
| 23 | SENSE2 | passive | Sense resistor terminal for bridge 2; voltage must not exceed the ±0.5 V maximum rating. |
| 24 | VBB2 | power_in | Load supply for bridge 2, operating range 8 to 35 V. |
| 25 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | QFN-24(4x4) |
| Category | Others |
| Pins | 25 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage | VBB | | | 35 | V | | 2 |
| Output Current | IOUT | -2 | | 2 | A | | 2 |
| Logic Input Voltage | VIN | -0.3 | | 5.5 | V | | 2 |
| Logic Supply Voltage | VDD | -0.3 | | 5.5 | V | | 2 |
| Motor Outputs Voltage | | -2 | | 37 | V | | 2 |
| Sense Voltage | VSENSE | -0.5 | | 0.5 | V | | 2 |
| Reference Voltage | VREF | | | 5.5 | V | | 2 |
| Operating Ambient Temperature | TA | -20 | | 85 | °C | Range S | 2 |
| Maximum Junction Temperature | TJ(max) | | | 150 | °C | | 2 |
| Storage Temperature | Tstg | -55 | | 150 | °C | | 2 |
| Load Supply Voltage Range, operating | VBB | 8 | | 35 | V | Operating | 4 |
| Load Supply Voltage Range, sleep | VBB | 0 | | 35 | V | During Sleep Mode | 4 |
| Logic Supply Voltage Range | VDD | 3 | | 5.5 | V | Operating | 4 |
| Source Output On Resistance | RDSON | | 320 | 430 | mΩ | Source Driver, IOUT = -1.5 A | 4 |
| Sink Output On Resistance | RDSON | | 320 | 430 | mΩ | Sink Driver, IOUT = 1.5 A | 4 |
| Source Diode Forward Voltage | VF | | | 1.3 | V | Source Diode, IF = -1.5 A | 4 |
| Sink Diode Forward Voltage | VF | | | 1.3 | V | Sink Diode, IF = 1.5 A | 4 |
| Motor Supply Current | IBB | | | 4 | mA | fPWM < 50 kHz | 4 |
| Motor Supply Current, outputs disabled | IBB | | | 2 | mA | Operating, outputs disabled | 4 |
| Motor Supply Current, sleep | IBB | | | 10 | μA | Sleep Mode | 4 |
| Logic Supply Current | IDD | | | 8 | mA | fPWM < 50 kHz | 4 |
| Logic Supply Current, outputs off | IDD | | | 5 | mA | Outputs off | 4 |
| Logic Supply Current, sleep | IDD | | | 10 | μA | Sleep Mode | 4 |
| Logic Input Voltage high | VIN(1) | 0.7 | | | x VDD | printed as VDD × 0.7 | 4 |
| Logic Input Voltage low | VIN(0) | | | 0.3 | x VDD | printed as VDD × 0.3 | 4 |
| Logic Input Current high | IIN(1) | -20 | 1 | 20 | µA | VIN = VDD × 0.7; typ printed <1.0 | 4 |
| Logic Input Current low | IIN(0) | -20 | 1 | 20 | µA | VIN = VDD × 0.3; typ printed <1.0 | 4 |
| Logic Input Pull-down IN02 | RIN02 | | 100 | | kΩ | | 4 |
| Logic Input Pull-down IN12 | RIN12 | | 50 | | kΩ | | 4 |
| Logic Input Hysteresis | VHYS(IN) | 5 | 11 | 19 | % | As a % of VDD | 4 |
| Blank Time | tBLANK | 0.7 | 1 | 1.3 | μs | | 4 |
| Fixed Off-Time, OSC tied | tOFF | 20 | 30 | 40 | μs | OSC = VDD or GND | 4 |
| Fixed Off-Time, ROSC | tOFF | 23 | 30 | 37 | μs | ROSC = 25 kΩ | 4 |
| Reference Input Voltage Range | VREF | 0 | | 4 | V | | 4 |
| Reference Input Current | IREF | -3 | 0 | 3 | μA | | 4 |
| Current Trip-Level Error 33.3% | errI | | | 15 | % | VREF = 2 V, %ITripMAX = 33.3%; printed ±15 | 4 |
| Current Trip-Level Error 66.7% | errI | | | 5 | % | VREF = 2 V, %ITripMAX = 66.7%; printed ±5 | 4 |
| Current Trip-Level Error 100% | errI | | | 5 | % | VREF = 2 V, %ITripMAX = 100.00%; printed ±5 | 4 |
| Crossover Dead Time | tDT | 100 | 475 | 800 | ns | | 4 |
| Overcurrent Protection Threshold | IOCPST | 2.1 | | | A | | 4 |
| Thermal Shutdown Temperature | TTSD | | 165 | | °C | | 4 |
| Thermal Shutdown Hysteresis | TTSDHYS | | 15 | | °C | | 4 |
| VDD Undervoltage Lockout | VDDUVLO | 2.7 | 2.8 | 2.9 | V | VDD rising | 4 |
| VDD Undervoltage Hysteresis | VDDUVLOHYS | | 90 | | mV | | 4 |
| Package Thermal Resistance (ES) | RθJA | | 37 | | °C/W | ES package; estimated, on 4-layer PCB, based on JEDEC standard, still air | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | thermal dissipation and are lead (Pb) free (suffix -T), with 100% matte tin plated leadframes. | 1 |
## CAD (KiCad official)
- Symbol: `A4986SESTR-T`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files: `a4986sestr-t-etched.step` / `a4986sestr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a4986sestr-t.step` / `a4986sestr-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a4986sestr-t-datasheet.pdf) (17 pp, sha256 `ff5b906680415f46`, retrieved 2026-11-02, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/a4986sestr-t-datasheet.pdf)