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A4980KLPTR-T

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Allegro MicroSystems, LLC Motor Driver ICs, TSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A4980KLPTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · TSSOP-28-EP

A4980KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENSA passive Current sense node for bridge A; connect a sense resistor between SENSA and PGND, with sense voltage limited to -0.3 to 1 V.
2 STRn input Serial data strobe and serial access enable; when high, SCK and SDI activity is ignored and SDO is high impedance (-0.3 to 6 V).
3 DIR input Direction logic input; direction changes on the next STEP rising edge, and it has no effect when using the serial interface (-0.3 to 6 V).
4 OAP output Bridge A positive output for motor phase A, rated -0.3 to VBB, with positive current flowing from OAM to OAP.
5 OSC input Oscillator input; tie to AGND for the internal 4 MHz oscillator, connect a resistor to VDD to set the frequency, or drive an external 3 to 5 MHz clock.
6 SDI input Serial data input, 16-bit word MSB first, latched on the SCK rising edge (-0.3 to 6 V).
7 AGND power_in Analog reference ground, a quiet return for measurement and input references that must be connected to PGND externally.
8 REF input Reference input voltage setting the absolute maximum current for both phases (0.8 to 2 V); defaults to the internal reference when tied to VDD.
9 SCK input Serial interface clock; data is latched on the rising edge, with 16 rising edges required per write and SCK held high when STRn changes.
10 VDD power_in Logic supply of 3 to 5.5 V, compatible with 3.3 V and 5 V logic, to be decoupled with a 100 nF ceramic capacitor.
11 OBP output Bridge B positive output for motor phase B, rated -0.3 to VBB, with positive current flowing from OBM to OBP.
12 MS1 input Microstep resolution select input, ORed with the MS1 bit in Configuration Register 0 (-0.3 to 6 V).
13 MS0 input Microstep resolution select input, ORed with the MS0 bit in Configuration Register 0 (-0.3 to 6 V).
14 SENSB passive Current sense node for bridge B; connect a sense resistor between SENSB and PGND, with sense voltage limited to -0.3 to 1 V.
15 VBBB power_in Motor supply for bridge B, which also supplies the internal regulators and charge pump, rated -0.3 to 50 V and connected to VBBA.
16 DIAG output Diagnostic output selected via Configuration Register 1, defaulting to a low-true fault output (-0.3 to 6 V).
17 SDO tri_state Serial data output that is high impedance when STRn is high and outputs the diagnostic register Fault flag when STRn goes low.
18 OBM output Bridge B negative output for motor phase B, rated -0.3 to VBB.
19 STEP input Step logic input where the motor advances on the rising edge, a filtered input with hysteresis (-0.3 to 6 V).
20 VREG power_out Regulated supply for bridge gate drive, typically 7.2 V, to be decoupled to ground with a 220 nF ceramic capacitor.
21 PGND power_in Digital and power ground, to be connected to supply ground and AGND.
22 VCP passive Above-supply voltage for high-side drive, with a 100 nF ceramic capacitor connected between VCP and VBB as the pump reservoir.
23 CP1 passive Charge pump capacitor terminal, with a 100 nF (50 V) ceramic capacitor connected between CP1 and CP2.
24 CP2 passive Charge pump capacitor terminal, with a 100 nF (50 V) ceramic capacitor connected between CP1 and CP2.
25 OAM output Bridge A negative output for motor phase A, rated -0.3 to VBB.
26 ENABLE input Bridge enable input; when low it turns off all output bridge FETs while internal logic continues to follow input commands.
27 RESETn input Chip reset that resets faults when pulsed low and forces sleep when held low longer than the 10 µs reset shutdown width.
28 VBBA power_in Motor supply for bridge A, which also supplies the internal regulators and charge pump, rated -0.3 to 50 V and connected to VBBB.
29 PAD power_in Exposed thermal pad that must be connected to ground and soldered to the board for thermal performance.

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package TSSOP-28-EP
Category Power Management ICs
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage (absolute max) VBBx -0.3 50 V Applies to VBBA and VBBB 2
Logic Supply Voltage (absolute max) VDD -0.3 6 V 2
Ambient Operating Temperature Range TA -40 150 °C Range K; limited by power dissipation 2
Maximum Continuous Junction Temperature TJ(max) 150 °C 2
Transient Junction Temperature TtJ 175 °C Overtemperature event not exceeding 10 s, lifetime duration not exceeding 10 hours 2
Storage Temperature Range Tstg -55 150 °C 2
Package Thermal Resistance Junction to Ambient RθJA 28 ºC/W 4-layer PCB based on JEDEC standard 2
Package Thermal Resistance Junction to Ambient RθJA 32 ºC/W 2-layer PCB with 24.52 cm2 of copper area each side 2
Package Thermal Resistance Junction to Pad RθJP 2 ºC/W 2
Load Supply Voltage Range VBB 0 50 V Functional 5
Load Supply Voltage Range VBB 3.3 V Outputs Driving (max VBBOV) 5
Load Supply Quiescent Current IBBQ 4 mA ENABLE = 0 5
Load Supply Quiescent Current IBBQ 1 10 µA Sleep mode 5
Logic Supply Voltage Range VDD 3 5.5 V 5
Logic Supply Quiescent Current IDDQ 5 mA ENABLE = 0 5
Logic Supply Quiescent Current IDDQ 5.5 mA ENABLE=0, VDD > 5 V 5
Logic Supply Quiescent Current IDDQ 4 15 µA Sleep mode 5
Internal Regulator Dropout Voltage VREGDO 100 200 mV ENABLE = 0, RESETn = 1, VBB > 3.5 V 5
High-Side On-Resistance RONH 500 600 mΩ VBB = 13.5 V, IOUT = -1 A, TJ = 25°C 5
High-Side On-Resistance RONH 900 1100 mΩ VBB = 13.5 V, IOUT = -1 A, TJ = 150°C 5
High-Side On-Resistance RONH 625 750 mΩ VBB = 7 V, IOUT = -1 A, TJ = 25°C 5
High-Side Body Diode Forward Voltage VFH 1.4 V IF = 1 A 5
Low-Side On-Resistance RONL 500 600 mΩ VBB = 13.5 V, IOUT = 1 A, TJ = 25°C 5
Low-Side On-Resistance RONL 900 1100 mΩ VBB = 13.5 V, IOUT = 1 A, TJ = 150°C 5
Low-Side On-Resistance RONL 625 750 mΩ VBB = 7 V, IOUT = 1 A, TJ = 25°C 5
Low-Side Body Diode Forward Voltage VFL 1.4 V IF = -1 A 5
Output Leakage Current ILO -120 -65 µA ENABLE = 0, RESETn = 1, VO = VBB 5
Output Leakage Current ILO -200 -120 µA ENABLE = 0, RESETn = 1, VO = 0 V 5
Output Leakage Current ILO 20 µA ENABLE = 0, RESETn = 0, VO = VBB 5
Output Leakage Current ILO -20 µA ENABLE = 0, RESETn = 0, VO = 0 V 5
Internal Oscillator Frequency fOSC 3.2 4 4.8 MHz OSC = AGND 5
Internal Oscillator Frequency fOSC 3.6 4.4 MHz 51 kΩ from OSC to VDD 5
External Oscillator Frequency Range fEXT 3 5 MHz 5
Reference Input Voltage VREF 0.8 2 V 5
Internal Reference Voltage VREFint 1.1 1.2 1.3 V REF tied to VDD 5
Reference Input Current IREF -3 0 3 µA 6
Current Trip Point Error EITrip 5 % VREF = 2 V, MXI0 = MXI1 = 1 (±5) 6
Input Low Voltage VIL 0.3 V × VDD 6
Input Low Voltage VIL 0.28 V VDD > 4.5 V, × VDD 6
Input High Voltage VIH 0.7 V × VDD 6
Input Hysteresis VIhys 250 500 mV 6
Input Current (Except RESETn) IIN -1 1 µA 0 V < VIN < VDD 6
Output Low Voltage VOL 0.2 0.4 V IOL = 2 mA 6
Output High Voltage VOH -0.4 -0.2 V IOL = -2 mA; printed VDD-0.4 / VDD-0.2 6
Output Leakage (SDO) IO -1 1 µA 0 V < VO < VDD, STRn = 1 6
Reset Pulse Width tRST 0.2 4.5 µs 6
Reset Shutdown Width tRSD 10 µs 6
Clock High Time tSCKH 50 ns A in figure 1 6
Clock Low Time tSCKL 50 ns B in figure 1 6
Strobe Lead Time tSTLD 30 ns C in figure 1 6
Strobe Lag Time tSTLG 30 ns D in figure 1 6
Strobe High Time tSTRH 300 ns E in figure 1 6
Data Out Enable Time tSDOE 40 ns F in figure 1 6
Data Out Disable Time tSDOD 30 ns G in figure 1 6
Data Out Valid Time from Clock Falling tSDOV 40 ns H in figure 1 6
Data Out Hold Time from Clock Falling tSDOH 5 ns I in figure 1 6
Data In Set-Up Time to Clock Rising tSDIS 15 ns J in figure 1 6
Data In Hold Time From Clock Rising tSDIH 10 ns K in figure 1 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin lead (Pb) free with 100% matte-tin leadframe plating. A4980-DS, Rev. 4 1

CAD (KiCad official)

  • Symbol: A4980KLPTR-T
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: TSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: a4980klptr-t-etched.step / a4980klptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4980klptr-t.step / a4980klptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (46 pp, sha256 9c15a9f98e3c9e4f, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF