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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

A4964KJPTR-T

Allegro MicroSystems LLC · Brushless DC (BLDC) Motor Driver · QFP-32(7x7)

A4964KJPTR-T from Allegro MicroSystems LLC, in a QFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DIAG	output	Programmable diagnostic output; can be shorted to ground or VBAT without damage.
2	VLR	power_out	VLR logic regulator output, selectable to 3.3 or 5 V; requires ≥1 µF ceramic decoupling capacitor (ESR ≤250 mΩ) to GND for stability.
3	STRn	input	Serial strobe and chip select logic input with pull-up; when high, disables serial clock and data activity and forces SDO to high impedance.
4	SCK	input	Serial clock logic input with pull-down; data is latched from SDI on rising edge; must be held high when STRn changes.
5	SDI	input	Serial data logic input with pull-down for MSB-first 16-bit serial word transfer.
6	WDOG	input	Microcontroller watchdog logic input with pull-down; window watchdog with programmable minimum and maximum clock period.
7	SDO	output	Serial data logic output (high impedance when STRn is high); outputs diagnostic register bit 15 and fault flag.
8	MRSTn	output	Microcontroller reset logic output; held low until supplies are available and for 10 ms at power-up; resets microcontroller on watchdog failure.
9	CSM	input	Sense amplifier negative input; connect directly to one end of external current sense resistor using separate PCB trace.
10	CSP	input	Sense amplifier positive input; connect directly to other end of external current sense resistor using separate PCB trace.
11	LRX	output	LIN receive data logic output or PWM receive output; logic level referenced to VLR.
12	LTX	input	LIN transmit data logic input or fault diagnostic transmit input; logic level referenced to VLR.
13	LIN	bidirectional	LIN bus connection compliant with LIN 2.2A; can be used as PWM input in stand-alone mode or passed through to LRX output.
14	GND	power_in	Analog reference, digital and power ground; connect to supply ground with separate low-impedance traces for analog and digital returns.
15	GLC	output	Phase C low-side FET gate drive output; drives external N-channel MOSFET gate with regulated voltage.
16	GHC	output	Phase C high-side FET gate drive output; floats with respect to SC; drives external N-channel MOSFET gate.
17	SC	output	Phase C motor phase connection; carries motor phase current and serves as reference for high-side gate driver; also senses back-EMF.
18	CC	passive	Phase C bootstrap capacitor connection; positive supply for phase C high-side gate driver; connect external bootstrap capacitor between CC and SC.
19	GLB	output	Phase B low-side FET gate drive output; drives external N-channel MOSFET gate with regulated voltage.
20	GHB	output	Phase B high-side FET gate drive output; floats with respect to SB; drives external N-channel MOSFET gate.
21	SB	output	Phase B motor phase connection; carries motor phase current and serves as reference for high-side gate driver; also senses back-EMF.
22	CB	passive	Phase B bootstrap capacitor connection; positive supply for phase B high-side gate driver; connect external bootstrap capacitor between CB and SB.
23	GLA	output	Phase A low-side FET gate drive output; drives external N-channel MOSFET gate with regulated voltage.
24	GHA	output	Phase A high-side FET gate drive output; floats with respect to SA; drives external N-channel MOSFET gate.
25	SA	output	Phase A motor phase connection; carries motor phase current and serves as reference for high-side gate driver; also senses back-EMF.
26	CA	passive	Phase A bootstrap capacitor connection; positive supply for phase A high-side gate driver; connect external bootstrap capacitor between CA and SA.
27	VREG	power_out	Gate drive supply capacitor terminal; nominally 11 V regulated output; powers low-side gate drivers and charges bootstrap capacitors; requires large storage capacitor.
28	CP2	passive	Pump capacitor high terminal for charge pump; connect 470 nF ceramic capacitor between CP1 and CP2.
29	CP1	passive	Pump capacitor low terminal for charge pump; connect 470 nF ceramic capacitor between CP1 and CP2.
30	VBB	power_in	Main power supply input for internal regulators and charge pump; 5.5 to 50 V operating range; requires reverse polarity protection and 100 nF decoupling capacitor.
31	IG	input	Ignition switch input with internal pull-down; enables logic regulator and microcontroller power when driven high; tie to GND when unused.
32	VBRG	input	High-side drain voltage sense input; measures voltage at drain of high-side MOSFETs in bridge for accurate diagnostics and overvoltage detection.

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems LLC
Package	QFP-32(7x7)
Category	Motor Driver ICs
Pins	32

CAD (KiCad official)

Symbol: A4964KJPTR-T
Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
3D model: QFP-32(7x7) (KiCad packages3D, STEP)
3D model files: a4964kjptr-t-etched.step / a4964kjptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4964kjptr-t.step / a4964kjptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems LLC datasheet (92 pp, sha256 53da98bac1dbb4e0, retrieved 2026-09-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF