component

A4956KLPTR-T

Public Made by Adom

by adom

Allegro MicroSystems, LLC Motor Driver ICs, TSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chipa4956klptr-tfactory-2.0.0extractor-text

Verified A4956KLPTR-T

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 21 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: A4956KLPTR-T · TSSOP-20-EP · 21 pins
  • ✓copper: 21 copper pads, none touching another net
  • ✓datasheet: all 21 pin names found in the 11-page datasheet
  • ✓distributor: lcsc C2688272, digikey 620-A4956KLPTR-TTR-ND, mouser 250-A4956KLPTR-T
  • ✓family: TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-6w1qjm0q/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.10)
  • ✓pads: 21 pins = 21 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 21 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ a4956klptr-t.kicad_sym✓ a4956klptr-t.kicad_mod✓ a4956klptr-t.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
a4956klptr-t / README.md
History Download
Ray Publish 0.1.0 08c58a8 3d ago

A4956KLPTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · TSSOP-20-EP

A4956KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground terminal for the device, listed in the terminal table as Ground.
2 AIOUT output Analog output proportional to VSENSE, with a gain of 9 to 11 V/V (VAIOUT/VSENSE for VSENSE = 50 to 200 mV) and an output impedance of 0.75 to 1.45 kΩ.
3 OCLn output Open-drain overcurrent and VDS-fault flag that is driven low during PWM current limiting or a latched VDS fault, with leakage of 5 µA maximum at 5 V in normal operation.
4 VREF power_in Analog overcurrent reference input with a range of 0 to 2.5 V that sets the peak current via I = VREF / (10 × RSENSE); absolute maximum rating is -0.3 to 5.5 V.
5 ENABLE input Digital enable input with VIH minimum of 2.0 V, VIL maximum of 0.8 V, 30 to 70 kΩ pull-down, and an absolute maximum rating of -0.3 to 5.5 V; held low for about 1 ms enters standby.
6 PHASE input Digital phase input that selects bridge direction, with VIH minimum of 2.0 V, VIL maximum of 0.8 V, and an absolute maximum rating of -0.3 to 5.5 V.
7 RC passive Terminal for an external RC network to ground that sets the fixed off-time and blank-time, with RRC of 12 to 100 kΩ and CRC of 470 to 1500 pF for the off-time equation.
8 ISET passive Terminal for a resistor to ground that sets the gate drive current, with RISET recommended between 15 and 150 kΩ.
9 MODE input Digital mode input that selects slow decay when logic high or fast decay when logic low on ENABLE low, with an absolute maximum rating of -0.3 to 5.5 V.
10 SENSE passive Sense resistor connection and low-side gate return, with an absolute maximum rating of -0.5 to 0.5 V (-4 to 4 V for tW < 500 ns).
11 GLB output Low-side gate drive output for the B half-bridge, with VGL of 6.5 to 7.5 V at VBB of 8 to 50 V.
12 GLA output Low-side gate drive output for the A half-bridge, with VGL of 6.5 to 7.5 V at VBB of 8 to 50 V.
13 GHB output High-side gate drive output for the B half-bridge, with VGH of 6.5 to 7.5 V relative to VBB at VBB of 8 to 50 V.
14 SB passive High-side bridge reference for the B half-bridge, with motor output voltage VSx rated -2 to 52 V per the absolute maximum ratings.
15 GHA output High-side gate drive output for the A half-bridge, with VGH of 6.5 to 7.5 V relative to VBB at VBB of 8 to 50 V.
16 SA passive High-side bridge reference for the A half-bridge, with motor output voltage VSx rated -2 to 52 V per the absolute maximum ratings.
17 VCP power_out Charge pump reservoir capacitor connection, which is internally monitored so that a low VCP fault disables the outputs.
18 CP2 passive Charge pump terminal used to generate a supply above VBB for the high-side MOSFETs.
19 VBB power_in Load supply voltage with an absolute maximum rating of 50 V; the UVLO enable threshold is 5.10 to 5.40 V rising.
20 CP1 passive Charge pump terminal used to generate a supply above VBB for the high-side MOSFETs.
21 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package TSSOP-20-EP
Category Power Supply Chip
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage VBB 50 V 2
Motor Outputs VSx -2 52 V VSx, VSENSE; VBB, VSx 2
SENSE VSENSE -0.5 0.5 V 2
SENSE transient VSENSE -4 4 V tW < 500 ns 2
OCLn VOCLn -0.3 5.5 V 2
VREF VREF -0.3 5.5 V 2
ISET VISET -0.3 5.5 V 2
AIOUT VAIOUT -0.3 5.5 V 2
Logic Input Voltage Range VIN -0.3 5.5 V PHASE, ENABLE, MODE 2
Junction Temperature TJ 150 °C 2
Storage Temperature Range TS -55 150 °C 2
Operating Temperature Range TA -40 125 °C Range K 2
VBB Supply Current IBB 6 10 mA 4
VBB Supply Current, Standby IBB 5 µA SLEEPn = low, Standby Mode 4
High-Side Gate Drive Output VGH 6.5 6.8 7.5 V Relative to VBB, IGATE = 200 µA, VBB = 8 to 50 V 4
Low-Side Gate Drive Output VGL 6.5 6.8 7.5 V IGATE = 200 µA, VBB = 8 to 50 V 4
Gate Drive Pull-Up Current IGPU 21 30 39 mA RISET = 30 kΩ; VGH = VGL = 4 V 4
Gate Drive Pull-Down Current IGPD 47 68 89 mA RISET = 30 kΩ; VGH = VGL = 4 V 4
Passive Pull-Down Resistance RGPD 30 50 70 kΩ 4
Logic Output Voltage VOCLn 0.2 0.3 V I = 2 mA, overcurrent detected 4
Logic Output Leakage IOCLn 5 µA V = 5 V, normal operation 4
PWM Current Limit Flag Timer tOCLn 300 500 600 µs 4
Logic Input Voltage High VIH 2 V 4
Logic Input Voltage Low VIL 0.8 V 4
Logic Input Voltage Low, Standby VIL(STANDBY) 0.4 V Standby Mode, ENABLE input 4
Logic Input Pull-Down Resistor RPD 30 50 70 kΩ 4
VREF Input Current IVREF -5 5 µA VREF = 2.5 V 4
VREF Input Range VREF 0 2.5 V 4
Current Gain AV 9.5 10.5 V/V VREF / VSENSE, VREF = 2.5 V 4
Input Offset, SENSE VOSSENSE -10 10 mV 4
Blank-Time tBLK 2.1 3 3.9 µs RRC = 30 kΩ, CRC = 1 nF 4
Standby Timer 0.7 1 1.3 ms 4
Power-Up Delay tpu 50 300 µs Time until outputs are enabled 4
AIOUT Gain AIOUT 9 10 11 V/V VAIOUT / VSENSE, VSENSE = 50 to 200 mV 4
Input Offset, AIOUT VOSAIOUT -15 15 mV 4
AIOUT Output Impedance ROUT(AIOUT) 0.75 1 1.45 kΩ 4
UVLO Enable Threshold VBB(UVLO) 5.1 5.25 5.4 V VBB rising 4
UVLO Hysteresis VBB(UVLO,HYS) 200 300 350 mV 4
Thermal Shutdown Temperature TJTSD 150 165 185 °C Temperature increasing. 4
Sample-and-Hold Droop Rate VDROOP 1 mV/µs 4
High-Side Gate Drive Output at VBB = 5.5 V VGH 5.2 V Relative to VBB, IGATE = 200 µA, VBB = 5.5 V 4
Low-Side Gate Drive Output at VBB = 5.5 V VGL 5.4 V IGATE = 200 µA, VBB = 5.5 V 4
Dead-Time tDT 1000 ns 4
Logic Input Hysteresis VHYS 320 mV 4
Sample-and-Hold Accuracy VSH(ACC) 15 mV 4
VDS Threshold VDSTH 2 V 4
Fixed Off-Time tOFF 30 µs RRC = 30 kΩ, CRC = 1 nF 4
Percent Fast Decay PFD 13 % Internal PWM chop 4
Thermal Shutdown Hysteresis ΔTJ 30 °C Recovery = TJTSD, ΔTJ 4
Junction-to-Ambient Thermal Resistance, LP package RθJA 28 °C/W 4-Layer PCB, 1 in.2 Cu 2

CAD (KiCad official)

  • Symbol: A4956KLPTR-T
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: a4956klptr-t-etched.step / a4956klptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4956klptr-t.step / a4956klptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (11 pp, sha256 28580082f838a5f5, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF