# A4956GLPTR-T

**Allegro MicroSystems, LLC** · Motor Driver ICs · TSSOP-20-EP

A4956GLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground return for the device; the datasheet gives no numeric limit for this pin. |
| 2 | AIOUT | output | Analog output proportional to VSENSE with a gain of 9 to 11 V/V (VSENSE = 50 to 200 mV) and an output impedance of 0.75 to 1.45 kΩ, absolute maximum -0.3 to 5.5 V. |
| 3 | OCLn | output | Open-drain overcurrent and VDS-fault flag output, driven low at up to 0.3 V with 2 mA sink, with absolute maximum -0.3 to 5.5 V. |
| 4 | VREF | power_in | Analog overcurrent reference input with a valid range of 0 to 2.5 V and absolute maximum -0.3 to 5.5 V; it sets the peak current limit via VREF/(10 × RSENSE). |
| 5 | ENABLE | input | Digital enable input with VIH minimum 2.0 V and VIL maximum 0.8 V; holding it low for about 1 ms (tSTB, typical) enters low-power standby mode. |
| 6 | PHASE | input | Digital phase input that sets the bridge direction, with VIH minimum 2.0 V, VIL maximum 0.8 V, and absolute maximum 5.5 V. |
| 7 | RC | passive | Connection for the external RC network to ground that sets fixed off-time and blank-time, using RRC of 12 to 100 kΩ and CRC of 470 to 1500 pF. |
| 8 | ISET | passive | A resistor from this terminal to ground sets the gate drive current, with RISET specified between 15 and 150 kΩ. |
| 9 | MODE | input | Digital input that selects slow decay (logic high) or fast decay (logic low) when ENABLE goes low, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 10 | SENSE | passive | Sense resistor connection and low-side gate return, rated -0.5 to 0.5 V continuous and -4 to 4 V for tW < 500 ns. |
| 11 | GLB | output | Low-side gate drive output for half-bridge B, specified at 6.5 to 7.5 V (VBB = 8 to 50 V, IGATE = 200 µA). |
| 12 | GLA | output | Low-side gate drive output for half-bridge A, specified at 6.5 to 7.5 V (VBB = 8 to 50 V, IGATE = 200 µA). |
| 13 | GHB | output | High-side gate drive output for half-bridge B, specified at 6.5 to 7.5 V relative to VBB (VBB = 8 to 50 V, IGATE = 200 µA). |
| 14 | SB | passive | High-side bridge reference connection for half-bridge B, with the motor output voltage range of -2 to 52 V relative to VBB. |
| 15 | GHA | output | High-side gate drive output for half-bridge A, specified at 6.5 to 7.5 V relative to VBB (VBB = 8 to 50 V, IGATE = 200 µA). |
| 16 | SA | passive | High-side bridge reference connection for half-bridge A, with the motor output voltage range of -2 to 52 V relative to VBB. |
| 17 | VCP | passive | Charge pump reservoir capacitor connection, monitored internally, with outputs disabled on a low-VCP fault. |
| 18 | CP2 | passive | Charge pump terminal for the internal charge pump generating the high-side gate supply above VBB. |
| 19 | VBB | power_in | Load supply voltage with absolute maximum 50 V; the internal UVLO enables at 5.10 to 5.40 V (rising). |
| 20 | CP1 | passive | Charge pump terminal for the internal charge pump generating the high-side gate supply above VBB. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-20-EP |
| Category | Power Management ICs |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage | VBB |  |  | 50 | V |  | 2 |
| Motor Outputs | VSx | -2 |  | 52 | V | VSx, VSENSE; VBB, VSx | 2 |
| SENSE | VSENSE | -0.5 |  | 0.5 | V |  | 2 |
| SENSE transient |  | -4 |  | 4 | V | tW < 500 ns | 2 |
| OCLn | VOCLn | -0.3 |  | 5.5 | V |  | 2 |
| VREF | VREF | -0.3 |  | 5.5 | V |  | 2 |
| ISET | VISET | -0.3 |  | 5.5 | V |  | 2 |
| AIOUT | VAIOUT | -0.3 |  | 5.5 | V |  | 2 |
| Logic Input Voltage Range | VIN | -0.3 |  | 5.5 | V | PHASE, ENABLE, MODE | 2 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 2 |
| Storage Temperature Range | TS | -55 |  | 150 | °C |  | 2 |
| Operating Temperature Range, Range G | TA | -40 |  | 105 | °C | Range G (this part; A4956GLPTR-T) | 2 |
| Thermal resistance, junction to ambient, LP (eTSSOP) package | RθJA |  | 28 |  | °C/W | 4-Layer PCB, 1 in.2 Cu | 2 |
| Supply voltage operating range | VBB | 5.5 |  | 50 | V | Electrical characteristics header: Range G at TJ = 25°C, VBB = 5.5 to 50 V, unless otherwise specified | 4 |
| VBB Supply Current | IBB |  | 6 | 10 | mA |  | 4 |
| Standby supply current | IBB |  |  | 5 | µA | SLEEPn = low, Standby Mode | 4 |
| High-Side Gate Drive Output | VGH | 6.5 | 6.8 | 7.5 | V | Relative to VBB, IGATE = 200 µA, VBB = 8 to 50 V | 4 |
| Low-Side Gate Drive Output | VGL | 6.5 | 6.8 | 7.5 | V | IGATE = 200 µA, VBB = 8 to 50 V | 4 |
| Gate Drive Pull-Up Current | IGPU | 21 | 30 | 39 | mA | RISET = 30 kΩ; VGH = VGL = 4 V | 4 |
| Gate Drive Pull-Down Current | IGPD | 47 | 68 | 89 | mA | RISET = 30 kΩ; VGH = VGL = 4 V | 4 |
| Passive Pull-Down Resistance | RGPD | 30 | 50 | 70 | kΩ |  | 4 |
| Logic Output Voltage | VOCLn |  | 0.2 | 0.3 | V | I = 2 mA, overcurrent detected | 4 |
| Logic Output Leakage | IOCLn |  |  | 5 | µA | V = 5 V, normal operation | 4 |
| PWM Current Limit Flag Timer | tOCLn | 300 | 500 | 600 | µs |  | 4 |
| Logic Input Voltage High | VIH | 2 |  |  | V |  | 4 |
| Logic Input Voltage Low | VIL |  |  | 0.8 | V |  | 4 |
| Logic Input Voltage Low, standby | VIL(STANDBY) |  |  | 0.4 | V | Standby Mode, ENABLE input | 4 |
| Logic Input Pull-Down Resistor | RPD | 30 | 50 | 70 | kΩ |  | 4 |
| VREF Input Current | IVREF | -5 |  | 5 | µA | VREF = 2.5 V | 4 |
| VREF Input Range | VREF | 0 |  | 2.5 | V |  | 4 |
| Current Gain | AV | 9.5 |  | 10.5 | V/V | VREF / VSENSE, VREF = 2.5 V | 4 |
| Input Offset, SENSE | VOSSENSE | -10 |  | 10 | mV |  | 4 |
| Blank-Time | tBLK | 2.1 | 3 | 3.9 | µs | RRC = 30 kΩ, CRC = 1 nF | 4 |
| Standby Timer |  | 0.7 | 1 | 1.3 | ms |  | 4 |
| Power-Up Delay | tpu |  | 50 | 300 | µs | Time until outputs are enabled | 4 |
| AIOUT Gain | AIOUT | 9 | 10 | 11 | V/V | VAIOUT / VSENSE, VSENSE = 50 to 200 mV | 4 |
| Input Offset, AIOUT | VOSAIOUT | -15 |  | 15 | mV |  | 4 |
| Sample-and-Hold Droop Rate | VDROOP |  |  | 1 | mV/µs |  | 4 |
| AIOUT Output Impedance | ROUT(AIOUT) | 0.75 | 1 | 1.45 | kΩ |  | 4 |
| UVLO Enable Threshold | VBB(UVLO) | 5.1 | 5.25 | 5.4 | V | VBB rising | 4 |
| UVLO Hysteresis | VBB(UVLO,HYS) | 200 | 300 | 350 | mV |  | 4 |
| Thermal Shutdown Temperature | TJTSD | 150 | 165 | 185 | °C | Temperature increasing. | 4 |

## CAD (KiCad official)

- Symbol: `A4956GLPTR-T`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `a4956glptr-t-etched.step` / `a4956glptr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a4956glptr-t.step` / `a4956glptr-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a4956glptr-t-datasheet.pdf) (11 pp, sha256 `139b044dfc18bf37`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a4956glptr-t-datasheet.pdf)