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A4955KLPTR-T

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Allegro MicroSystems, LLC Gate Drive ICs, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsa4955klptr-tfactory-2.0.0extractor-text

Verified A4955KLPTR-T

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 21 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: A4955KLPTR-T · HTSSOP-20-EP · 21 pins
  • ✓copper: 21 copper pads, none touching another net
  • ✓datasheet: all 21 pin names found in the 11-page datasheet
  • ✓distributor: lcsc C2688271, digikey 620-1771-2-ND, mouser 250-A4955KLPTR-T
  • ✓family: TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-s81gj8sf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.10)
  • ✓pads: 21 pins = 21 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 21 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ a4955klptr-t.kicad_sym✓ a4955klptr-t.kicad_mod✓ a4955klptr-t.step
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Ray Publish 0.1.0 4cf8a30 3d ago

A4955KLPTR-T

Allegro MicroSystems, LLC · Gate Drive ICs · HTSSOP-20-EP

A4955KLPTR-T from Allegro MicroSystems, LLC, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground terminal for the device.
2 AIOUT output Analog output proportional to VSENSE, with AIOUT/VSENSE gain of 9 to 11 V/V (10 typical) for VSENSE = 50 to 200 mV.
3 OCLn output Overcurrent and overvoltage flag, open-drain output driven low during current limiting or a VDS fault, with output voltage of 0.3 V max at 2 mA when overcurrent is detected.
4 VREF power_in Analog overcurrent-protection reference input with a range of 0 to 2.5 V.
5 IN2 input Digital logic input IN2 with VIH minimum 2.0 V, VIL maximum 0.8 V, and internal pull-down of 30 to 70 kΩ.
6 IN1 input Digital logic input IN1 with VIH minimum 2.0 V, VIL maximum 0.8 V, and internal pull-down of 30 to 70 kΩ.
7 RC passive Terminal to set blank-time and off-time through a resistor and capacitor to ground, with RRC of 12 to 100 kΩ and CRC of 470 to 1500 pF.
8 ISET passive Terminal to set gate drive current through a resistor to ground, which should be between 15 and 150 kΩ.
9 SLEEPn input Active-low sleep input, with VIL(SLEEPn) maximum of 0.4 V; driving it low activates standby mode.
10 SENSE passive Sense resistor connection and low-side gate return, with absolute maximum range of -0.5 to 0.5 V (-4 to 4 V for tW < 500 ns).
11 GLB output Low-side gate drive output for the B-side external MOSFET, with VGL of 6.5 to 7.5 V (6.8 V typical) at VBB = 8 to 50 V.
12 GLA output Low-side gate drive output for the A-side external MOSFET, with VGL of 6.5 to 7.5 V (6.8 V typical) at VBB = 8 to 50 V.
13 GHB output High-side gate drive output for the B-side external MOSFET, with VGH of 6.5 to 7.5 V relative to VBB at VBB = 8 to 50 V.
14 SB passive High-side bridge reference for the B half-bridge; the absolute rating for VSx - VSENSE is -2 to 52 V.
15 GHA output High-side gate drive output for the A-side external MOSFET, with VGH of 6.5 to 7.5 V relative to VBB at VBB = 8 to 50 V.
16 SA passive High-side bridge reference for the A half-bridge; the absolute rating for VSx - VSENSE is -2 to 52 V.
17 VCP power_out Charge pump reservoir capacitor connection, which is internally monitored, with outputs disabled on a VCP fault.
18 CP2 passive Charge pump terminal.
19 VBB power_in Load supply voltage with absolute maximum of 50 V and UVLO enable threshold of 5.10 to 5.40 V (VBB rising).
20 CP1 passive Charge pump terminal.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package HTSSOP-20-EP
Category Power Management ICs
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage VBB 50 V 2
Motor Outputs VSx -2 52 V VSx, VSENSE; VBB, VSx 2
SENSE VSENSE -0.5 0.5 V 2
SENSE VSENSE -4 4 V tW < 500 ns 2
OCLn VOCLn -0.3 5.5 V 2
VREF VREF -0.3 5.5 V 2
ISET VISET -0.3 5.5 V 2
AIOUT VAIOUT -0.3 5.5 V 2
Logic Input Voltage Range VIN -0.3 5.5 V SLEEPn, IN1, IN2 2
Junction Temperature TJ 150 °C 2
Storage Temperature Range TS -55 150 °C 2
Operating Temperature Range TA -40 125 °C Range K 2
VBB Supply Current IBB 6 10 mA 4
VBB Supply Current (standby) IBB 5 µA SLEEPn = low, Standby Mode 4
High-Side Gate Drive Output VGH 6.5 6.8 7.5 V Relative to VBB, IGATE = 200 µA, VBB = 8 to 50 V 4
Low-Side Gate Drive Output VGL 6.5 6.8 7.5 V IGATE = 200 µA, VBB = 8 to 50 V 4
Gate Drive Pull-Up Current IGPU 21 30 39 mA RISET = 30 kΩ; VGH = VGL = 4 V 4
Gate Drive Pull-Down Current IGPD 47 68 89 mA RISET = 30 kΩ; VGH = VGL = 4 V 4
Passive Pull-Down Resistance RGPD 30 50 70 kΩ 4
Logic Output Voltage VOCLn 0.2 0.3 V I = 2 mA, overcurrent detected 4
Logic Output Leakage IOCLn 5 µA V = 5 V, normal operation 4
PWM Current Limit Flag Timer tOCLn 300 500 600 µs 4
Logic Input Voltage (high) VIH 2 V 4
Logic Input Voltage (low) VIL 0.8 V 4
Logic Input Voltage (SLEEPn) VIL(SLEEPn) 0.4 V SLEEPn input 4
Logic Input Pull-Down Resistor RPD 30 50 70 kΩ 4
VREF Input Current IVREF -5 5 µA VREF = 2.5 V 4
VREF Input Range VREF 0 2.5 V 4
Current Gain AV 9.5 10.5 V/V VREF / VSENSE, VREF = 2.5 V 4
Input Offset, SENSE VOSSENSE -10 10 mV 4
Blank-Time tBLK 2.1 3 3.9 µs RRC = 30 kΩ, CRC = 1 nF 4
Power-Up Delay tpu 50 300 µs Time until outputs are enabled 4
AIOUT Gain AIOUT 9 10 11 V/V AIOUT/VSENSE, VSENSE = 50 to 200 mV 4
Input Offset, AIOUT VOSAIOUT -15 15 mV 4
Sample-and-Hold Droop Rate VDROOP 1 mV/µs 4
AIOUT Output Impedance ROUT(AIOUT) 0.75 1 1.45 kΩ 4
UVLO Enable Threshold VBB(UVLO) 5.1 5.25 5.4 V VBB rising 4
UVLO Hysteresis VBB(UVLO,HYS) 200 300 350 mV 4
Thermal Shutdown Temperature TJTSD 150 165 185 °C Temperature increasing 4
Thermal Resistance, junction to ambient (LP package) RθJA 28 °C/W 4-Layer PCB, 1 in.2 copper 2

CAD (KiCad official)

  • Symbol: A4955KLPTR-T
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: a4955klptr-t-etched.step / a4955klptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4955klptr-t.step / a4955klptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (11 pp, sha256 6d475e85d5bccd9d, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF