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A4955GLPTR-T

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Allegro MicroSystems LLC Brushed DC Motor Drivers, TSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A4955GLPTR-T

Allegro MicroSystems LLC · Brushed DC Motor Drivers · TSSOP-20-EP

A4955GLPTR-T from Allegro MicroSystems LLC, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference terminal for the device; the datasheet gives no electrical limits for this pin.
2 AIOUT output Analog output proportional to VSENSE with a gain of 9 to 11 V/V (10 V/V typical) and an output impedance of 0.75 to 1.45 kΩ, with an absolute maximum of -0.3 to 5.5 V.
3 OCLn output Open-drain overcurrent and VDS fault flag that is driven low during current limiting or a VDS fault, with a logic output voltage of 0.3 V max at 2 mA and an absolute maximum of -0.3 to 5.5 V.
4 VREF power_in Analog overcurrent reference input with an input range of 0 to 2.5 V and an absolute maximum of -0.3 to 5.5 V.
5 IN2 input Digital logic input for IN2 with VIH of 2.0 V min and VIL of 0.8 V max, an internal pull-down of 30 to 70 kΩ, and an absolute maximum of -0.3 to 5.5 V.
6 IN1 input Digital logic input for IN1 with VIH of 2.0 V min and VIL of 0.8 V max, an internal pull-down of 30 to 70 kΩ, and an absolute maximum of -0.3 to 5.5 V.
7 RC passive Terminal for the external RC network to ground that sets the fixed off-time and blank-time, with RRC of 12 to 100 kΩ and CRC of 470 to 1500 pF.
8 ISET passive Resistor terminal to ground that sets the gate drive current, with RISET between 15 and 150 kΩ.
9 SLEEPn input Active-low sleep input where a low level (VIL(SLEEPn) of 0.4 V max) puts the device into standby mode, with an absolute maximum of -0.3 to 5.5 V.
10 SENSE passive Sense resistor connection and low-side gate return, with VSENSE limited to -0.5 to 0.5 V (-4 to 4 V for tW < 500 ns).
11 GLB output Low-side gate drive output for the B half-bridge MOSFET, with VGL of 6.5 V min, 6.8 V typ and 7.5 V max at VBB = 8 to 50 V.
12 GLA output Low-side gate drive output for the A half-bridge MOSFET, with VGL of 6.5 V min, 6.8 V typ and 7.5 V max at VBB = 8 to 50 V.
13 GHB output High-side gate drive output for the B half-bridge MOSFET, with VGH of 6.5 V min, 6.8 V typ and 7.5 V max relative to VBB at VBB = 8 to 50 V.
14 SB passive High-side bridge reference for the B half-bridge, with the motor output VSx limited to -2 to 52 V.
15 GHA output High-side gate drive output for the A half-bridge MOSFET, with VGH of 6.5 V min, 6.8 V typ and 7.5 V max relative to VBB at VBB = 8 to 50 V.
16 SA passive High-side bridge reference for the A half-bridge, with the motor output VSx limited to -2 to 52 V.
17 VCP passive Charge pump reservoir capacitor connection that is internally monitored, with outputs disabled on a VCP fault.
18 CP2 passive Charge pump terminal for the charge pump capacitor connection.
19 VBB power_in Load supply voltage with a 50 V operating limit (absolute maximum 50 V) and an undervoltage enable threshold of 5.10 to 5.40 V rising.
20 CP1 passive Charge pump terminal for the charge pump capacitor connection.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems LLC
Package TSSOP-20-EP
Category Motor Driver ICs
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage VBB 50 V 2
Motor Outputs VSx -2 52 V VSx, VSENSE; VBB, VSx 2
SENSE VSENSE -0.5 0.5 V 2
SENSE transient VSENSE -4 4 V tW < 500 ns 2
OCLn VOCLn -0.3 5.5 V 2
VREF VREF -0.3 5.5 V 2
ISET VISET -0.3 5.5 V 2
AIOUT VAIOUT -0.3 5.5 V 2
Logic Input Voltage Range VIN -0.3 5.5 V SLEEPn, IN1, IN2 2
Junction Temperature TJ 150 °C 2
Storage Temperature Range TS -55 150 °C 2
Operating Temperature Range TA -40 105 °C Range G 2
Supply voltage range for electrical characteristics VBB 5.5 50 V Valid for Temperature Range G version at TJ = 25°C, unless otherwise specified 4
ISET resistor RISET 15 150 kΩ 6
Off-time timing capacitor CRC 470 1500 pF Range for fixed off-time approximation 6
Off-time timing resistor RRC 12 100 kΩ Range for fixed off-time approximation 6
VBB Supply Current IBB 6 10 mA 4
VBB Supply Current in Standby IBB 5 µA SLEEPn = low, Standby Mode 4
High-Side Gate Drive Output VGH 6.5 6.8 7.5 V Relative to VBB, IGATE = 200 µA, VBB = 8 to 50 V 4
High-Side Gate Drive Output VGH 5.2 V Relative to VBB, IGATE = 200 µA, VBB = 5.5 V 4
Low-Side Gate Drive Output VGL 6.5 6.8 7.5 V IGATE = 200 µA, VBB = 8 to 50 V 4
Low-Side Gate Drive Output VGL 5.4 V IGATE = 200 µA, VBB = 5.5 V 4
Gate Drive Pull-Up Current IGPU 21 30 39 mA RISET = 30 kΩ; VGH = VGL = 4 V 4
Gate Drive Pull-Down Current IGPD 47 68 89 mA RISET = 30 kΩ; VGH = VGL = 4 V 4
Passive Pull-Down Resistance RGPD 30 50 70 kΩ 4
Logic Output Voltage VOCLn 0.2 0.3 V I = 2 mA, overcurrent detected 4
Logic Output Leakage IOCLn 5 µA V = 5 V, normal operation 4
PWM Current Limit Flag Timer tOCLn 300 500 600 µs 4
Logic Input Voltage high VIH 2 V 4
Logic Input Voltage low VIL 0.8 V 4
Logic Input Voltage low, SLEEPn input VIL(SLEEPn) 0.4 V SLEEPn input 4
Logic Input Pull-Down Resistor RPD 30 50 70 kΩ 4
VREF Input Current IVREF -5 5 µA VREF = 2.5 V 4
VREF Input Range VREF 0 2.5 V 4
Current Gain AV 9.5 10.5 V/V VREF / VSENSE, VREF = 2.5 V 4
Input Offset, SENSE VOSSENSE -10 10 mV 4
Blank-Time tBLK 2.1 3 3.9 µs RRC = 30 kΩ, CRC = 1 nF 4
Power-Up Delay tpu 50 300 µs Time until outputs are enabled 4
AIOUT Gain AIOUT 9 10 11 V/V AIOUT/VSENSE, VSENSE = 50 to 200 mV 4
Input Offset, AIOUT VOSAIOUT -15 15 mV 4
Sample-and-Hold Droop Rate VDROOP 1 mV/µs 4
AIOUT Output Impedance ROUT(AIOUT) 0.75 1 1.45 kΩ 4
UVLO Enable Threshold VBB(UVLO) 5.1 5.25 5.4 V VBB rising 4
UVLO Hysteresis VBB(UVLO,HYS) 200 300 350 mV 4
Thermal Shutdown Temperature TJTSD 150 165 185 °C Temperature increasing 4
Dead-Time tDT 1000 ns 4
Sample-and-Hold Accuracy VSH(ACC) 15 mV 4
Logic Input Hysteresis VHYS 320 mV 4
Fixed Off-Time tOFF 30 µs RRC = 30 kΩ, CRC = 1 nF 4
Percent Fast Decay PFD 13 % Internal PWM chop 4
VDS Threshold VDSTH 2 V 4
Thermal Shutdown Hysteresis ΔTJ 30 °C Recovery = TJTSD, ΔTJ 4
Junction-to-ambient thermal resistance, LP package RθJA 28 °C/W 4-Layer PCB, 1 in.2 copper 2

CAD (KiCad official)

  • Symbol: A4955GLPTR-T
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: TSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: a4955glptr-t-etched.step / a4955glptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4955glptr-t.step / a4955glptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems LLC datasheet (11 pp, sha256 3b297e0745286756, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF