# A4955GESTR-T

**Allegro MicroSystems LLC** · Brushed DC Motor Drivers · QFN-20-EP(4x4)

A4955GESTR-T from Allegro MicroSystems LLC, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ISET | passive | Terminal to set gate drive current; a resistor from ISET to ground sets the gate current, and RISET should be between 15 and 150 kΩ. |
| 2 | SLEEPn | input | Active-low sleep input that puts the device into low-power standby mode, with a SLEEPn input low level of 0.4 V maximum. |
| 3 | SENSE | passive | Sense resistor connection and low-side gate return, with VSENSE limited to -0.5 to 0.5 V (-4 to 4 V for tW < 500 ns). |
| 4 | GLB | output | Low-side gate drive output for the B-side external MOSFET, specified at 6.5 to 7.5 V for VBB = 8 to 50 V. |
| 5 | GLA | output | Low-side gate drive output for the A-side external MOSFET, specified at 6.5 to 7.5 V for VBB = 8 to 50 V. |
| 6 | GHB | output | High-side gate drive output for the B-side external MOSFET, specified at 6.5 to 7.5 V relative to VBB for VBB = 8 to 50 V. |
| 7 | SB | output | High-side bridge reference connected to the B-side motor output, with the motor output VSx rated -2 to 52 V. |
| 8 | GHA | output | High-side gate drive output for the A-side external MOSFET, specified at 6.5 to 7.5 V relative to VBB for VBB = 8 to 50 V. |
| 9 | SA | output | High-side bridge reference connected to the A-side motor output, with the motor output VSx rated -2 to 52 V. |
| 10 | VCP | power_out | Charge pump reservoir capacitor connection, internally monitored so that a low VCP fault disables the outputs. |
| 11 | CP2 | passive | Charge pump terminal for the charge pump flying capacitor. |
| 12 | VBB | power_in | Load supply voltage, rated 50 V maximum, with UVLO enable threshold of 5.10 to 5.40 V (rising). |
| 13 | CP1 | passive | Charge pump terminal for the charge pump flying capacitor. |
| 14 | GND | power_in | Ground connection for the device. |
| 15 | AIOUT | output | Analog output proportional to VSENSE with a gain of 9 to 11 V/V and output impedance of 0.75 to 1.45 kΩ. |
| 16 | OCLn | output | Open-drain overcurrent and overvoltage (VDS fault) output flag, driven low during current limiting or a VDS fault, with output voltage of 0.3 V maximum at 2 mA. |
| 17 | VREF | power_in | Analog overcurrent reference input, with a VREF input range of 0 to 2.5 V. |
| 18 | IN2 | input | Digital logic input 2, with VIH of 2.0 V minimum, VIL of 0.8 V maximum, and absolute maximum range of -0.3 to 5.5 V. |
| 19 | IN1 | input | Digital logic input 1, with VIH of 2.0 V minimum, VIL of 0.8 V maximum, and absolute maximum range of -0.3 to 5.5 V. |
| 20 | RC | passive | Timing terminal for the RC network that sets the fixed off-time and blank-time, with RRC of 12 to 100 kΩ and CRC of 470 to 1500 pF. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | QFN-20-EP(4x4) |
| Category | Motor Driver ICs |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VBB Supply Current | IBB |  | 6 | 10 | mA |  | 4 |
| VBB Supply Current in Standby | IBB |  |  | 5 | µA | SLEEPn = low, Standby Mode | 4 |
| High-Side Gate Drive Output | VGH | 6.5 | 6.8 | 7.5 | V | Relative to VBB, IGATE = 200 µA, VBB = 8 to 50 V | 4 |
| Low-Side Gate Drive Output | VGL | 6.5 | 6.8 | 7.5 | V | IGATE = 200 µA, VBB = 8 to 50 V | 4 |
| Gate Drive Pull-Up Current | IGPU | 21 | 30 | 39 | mA | RISET = 30 kΩ; VGH = VGL = 4 V | 4 |
| Gate Drive Pull-Down Current | IGPD | 47 | 68 | 89 | mA | RISET = 30 kΩ; VGH = VGL = 4 V | 4 |
| Passive Pull-Down Resistance | RGPD | 30 | 50 | 70 | kΩ |  | 4 |
| Logic Output Voltage | VOCLn |  | 0.2 | 0.3 | V | I = 2 mA, overcurrent detected | 4 |
| Logic Output Leakage | IOCLn |  |  | 5 | µA | V = 5 V, normal operation | 4 |
| PWM Current Limit Flag Timer | tOCLn | 300 | 500 | 600 | µs |  | 4 |
| Logic Input Voltage (high) | VIH | 2 |  |  | V |  | 4 |
| Logic Input Voltage (low) | VIL |  |  | 0.8 | V |  | 4 |
| SLEEPn Logic Input Voltage (low) | VIL(SLEEPn) |  |  | 0.4 | V | SLEEPn input | 4 |
| Logic Input Pull-Down Resistor | RPD | 30 | 50 | 70 | kΩ |  | 4 |
| VREF Input Current | IVREF | -5 |  | 5 | µA | VREF = 2.5 V | 4 |
| VREF Input Range | VREF | 0 |  | 2.5 | V |  | 4 |
| Current Gain | AV | 9.5 |  | 10.5 | V/V | VREF / VSENSE, VREF = 2.5 V | 4 |
| Input Offset, SENSE | VOSSENSE | -10 |  | 10 | mV |  | 4 |
| Blank-Time | tBLK | 2.1 | 3 | 3.9 | µs | RRC = 30 kΩ, CRC = 1 nF | 4 |
| Power-Up Delay | tpu |  | 50 | 300 | µs | Time until outputs are enabled | 4 |
| AIOUT Gain | AIOUT | 9 | 10 | 11 | V/V | AIOUT/VSENSE, VSENSE = 50 to 200 mV | 4 |
| Input Offset, AIOUT | VOSAIOUT | -15 |  | 15 | mV |  | 4 |
| Sample-and-Hold Droop Rate | VDROOP |  |  | 1 | mV/µs |  | 4 |
| AIOUT Output Impedance | ROUT(AIOUT) | 0.75 | 1 | 1.45 | kΩ |  | 4 |
| UVLO Enable Threshold | VBB(UVLO) | 5.1 | 5.25 | 5.4 | V | VBB rising | 4 |
| UVLO Hysteresis | VBB(UVLO,HYS) | 200 | 300 | 350 | mV |  | 4 |
| Thermal Shutdown Temperature | TJTSD | 150 | 165 | 185 | °C | Temperature increasing | 4 |
| Load Supply Voltage | VBB |  |  | 50 | V |  | 2 |
| Motor Outputs | VSx | -2 |  | 52 | V | VSx, VSENSE; VBB, VSx | 2 |
| SENSE | VSENSE | -0.5 |  | 0.5 | V |  | 2 |
| SENSE transient | VSENSE | -4 |  | 4 | V | tW < 500 ns | 2 |
| OCLn Voltage | VOCLn | -0.3 |  | 5.5 | V |  | 2 |
| VREF Voltage | VREF | -0.3 |  | 5.5 | V |  | 2 |
| ISET Voltage | VISET | -0.3 |  | 5.5 | V |  | 2 |
| AIOUT Voltage | VAIOUT | -0.3 |  | 5.5 | V |  | 2 |
| Logic Input Voltage Range | VIN | -0.3 |  | 5.5 | V | SLEEPn, IN1, IN2 | 2 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 2 |
| Storage Temperature Range | TS | -55 |  | 150 | °C |  | 2 |
| Operating Temperature Range (Range G) | TA | -40 |  | 105 | °C | Range G | 2 |
| Junction-to-Ambient Thermal Resistance (ES package) | RθJA |  | 37 |  | °C/W | 4-Layer PCB, 1 in.2 copper | 2 |
| High-Side Gate Drive Output at low supply | VGH |  | 5.2 |  | V | Relative to VBB, IGATE = 200 µA, VBB = 5.5 V | 4 |
| Low-Side Gate Drive Output at low supply | VGL |  | 5.4 |  | V | IGATE = 200 µA, VBB = 5.5 V | 4 |
| Dead-Time | tDT |  | 1000 |  | ns |  | 4 |
| Logic Input Hysteresis | VHYS |  | 320 |  | mV |  | 4 |
| Percent Fast Decay | PFD |  | 13 |  | % | Internal PWM chop | 4 |
| Fixed Off-Time | tOFF |  | 30 |  | µs | RRC = 30 kΩ, CRC = 1 nF | 4 |
| Sample-and-Hold Accuracy | VSH(ACC) |  | 15 |  | mV |  | 4 |
| VDS Threshold | VDSTH |  | 2 |  | V |  | 4 |
| Thermal Shutdown Hysteresis | ΔTJ |  | 30 |  | °C | Recovery = TJTSD, ΔTJ | 4 |

## CAD (KiCad official)

- Symbol: `A4955GESTR-T`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`
- 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `a4955gestr-t-etched.step` / `a4955gestr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a4955gestr-t.step` / `a4955gestr-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems LLC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589837998499000320) (11 pp, sha256 `3b297e0745286756`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a4955gestr-t-datasheet.pdf)