Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	5d ago
viewers	a4950kljtr-t: viewers · Ray	5d ago
a4950kljtr-t-etched.glb	Publish 0.1.0 · Ray	5d ago
a4950kljtr-t-etched.step	a4950kljtr-t: factory component page (tier=lcsc) · Ray	5d ago
a4950kljtr-t-hero.glb	a4950kljtr-t: hero GLB from the etched model (keeps the MPN mark) · Ray	5d ago
a4950kljtr-t-hero.overlay.json	Publish 0.1.0 · Ray	5d ago
a4950kljtr-t.glb	Publish 0.1.0 · Ray	5d ago
a4950kljtr-t.kicad_mod	Publish 0.1.0 · Ray	5d ago
a4950kljtr-t.kicad_sym	Publish 0.1.0 · Ray	5d ago
a4950kljtr-t.lbr	Publish 0.1.0 · Ray	5d ago
a4950kljtr-t.step	Publish 0.1.0 · Ray	5d ago
package.json	Publish 0.1.0 · Ray	5d ago
page.json	Set visibility: public · Ray	5d ago
README.md	Publish 0.1.0 · Ray	5d ago

A4950KLJTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · SOIC-8-EP

A4950KLJTR-T from Allegro MicroSystems, LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground reference for the device; a star ground should be located as close to the A4950 as possible.
2	IN2	input	Logic input 2 for two-wire bridge control, with VIN(1) minimum 2.0 V, VIN(0) maximum 0.8 V, and typical pull-down resistance of 50 kΩ.
3	IN1	input	Logic input 1 for two-wire bridge control, with VIN(1) minimum 2.0 V, VIN(0) maximum 0.8 V, and typical pull-down resistance of 50 kΩ.
4	VREF	power_in	Analog input with a range of 0 to 5 V that sets the maximum PWM current limit through ITripMAX = 10 × VREF / RS.
5	VBB	power_in	Load supply voltage with an operating range of 8 V to 40 V and an absolute maximum rating of 40 V.
6	OUT1	output	DMOS full-bridge output 1, with motor outputs voltage rated −2 V to 42 V and output current rated 3.5 A at 100% duty cycle.
7	LSS	passive	Power return and sense resistor connection, which must not exceed ±500 mV at maximum load (absolute maximum sense voltage ±0.5 V).
8	OUT2	output	DMOS full-bridge output 2, with motor outputs voltage rated −2 V to 42 V and output current rated 3.5 A at 100% duty cycle.
9	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	SOIC-8-EP
Category	Power Management ICs
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Load Supply Voltage Range	VBB	8		40	V		3
Total RDS(on) Sink + Source	RDS(on)		0.6	0.8	Ω	IOUT = /2.5 A/, TJ = 25°C	3
Total RDS(on) Sink + Source	RDS(on)		1.1	1.5	Ω	IOUT = /2.5 A/, TJ = 150°C	3
Load Supply Current	IBB		10	20	mA	fPWM < 30 kHz	3
Load Supply Current in Low Power Standby mode	IBB			10	µA	Low Power Standby mode	3
Body Diode Forward Voltage (source diode)	Vf			1.5	V	Source diode, If = -2.5 A	3
Body Diode Forward Voltage (sink diode)	Vf			1.5	V	Sink diode, If = 2.5 A	3
Logic Input Voltage Range (high)	VIN(1)	2			V		3
Logic Input Voltage Range (low)	VIN(0)			0.8	V		3
Logic Input Voltage in Low Power Standby mode	VIN(STANDBY)			0.4	V	Low Power Standby mode	3
Logic Input Current (high)	IIN(1)		40	100	µA	VIN = 2.0 V	3
Logic Input Current (low)	IIN(0)		16	40	µA	VIN = 0.8 V	3
Input Hysteresis	VHYS		250	550	mV		3
Crossover Delay	tCOD	50		500	ns		3
VREF Input Voltage Range	VREF	0		5	V		3
Current Gain	AV	9.5		10.5	V/V	VREF / ISS, VREF = 5 V	3
Current Gain	AV	9		10	V/V	VREF / ISS, VREF = 2.5 V	3
Current Gain	AV	8		10	V/V	VREF / ISS, VREF = 1 V	3
Blank Time	tBLANK	2	3	4	µs		3
Constant Off-time	toff	16	25	34	µs		3
Standby Timer	tst		1	1.5	ms	IN1 = IN2 < VIN(STANDBY)	3
Power-Up Delay	tpu			30	µs		3
UVLO Enable Threshold	VBBUVLO	7	7.5	7.95	V	VBB increasing	3
Load Supply Voltage (absolute maximum)	VBB			40	V		2
Logic Input Voltage Range (absolute maximum)	VIN	-0.3		6	V		2
VREF Input Voltage Range (absolute maximum)	VREF	-0.3		6	V		2
Sense Voltage (LSS pin)	VS	-0.5		0.5	V		2
Motor Outputs Voltage	VOUT	-2		42	V		2
Output Current	IOUT			3.5	A	Duty cycle = 100%	2
Transient Output Current	iOUT			6	A	TW < 500 ns	2
Operating Temperature Range (Temperature Range K)	TA	-40		125	°C	Temperature Range K	2
Maximum Junction Temperature	TJ(max)			150	°C		2
Storage Temperature Range	Tstg	-55		150	°C		2
Package Thermal Resistance (2-layer PCB)	RθJA		62		ºC/W	On 2-layer PCB with 0.8 in2 exposed 2-oz. copper each side	2
Package Thermal Resistance (4-layer PCB)	RθJA		35		ºC/W	On 4-layer PCB based on JEDEC standard	2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	with exposed thermal pad (suffix LJ) that is lead (Pb) free, with 100% matte tin leadframe plating.	1

CAD (KiCad official)

Symbol: A4950KLJTR-T
Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
3D model: SOIC-8-EP (KiCad packages3D, STEP)
3D model files: a4950kljtr-t-etched.step / a4950kljtr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4950kljtr-t.step / a4950kljtr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (9 pp, sha256 70519785860fcb96, retrieved 2026-10-28, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF