component
A4949GLJTR-T
Public Made by Adomby adom
Allegro MicroSystems LLC Brushless DC (BLDC) Motor Driver, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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A4949GLJTR-T
Allegro MicroSystems LLC · Brushless DC (BLDC) Motor Driver · SOIC-8-EP
A4949GLJTR-T from Allegro MicroSystems LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference for the device; the datasheet gives no electrical limit for this pin. |
| 2 | OUTA | output | Motor phase A terminal driven by the sinusoidal gate drive, with total driver RDS(on) of 1.1 Ω typical at VBB = 12 V and overcurrent limiting (IOCL) of 1.4 to 1.8 A. |
| 3 | VBB | power_in | Input supply, specified for 4 to 18 V with an absolute maximum rating of 18 V and undervoltage lockout at 3.85 to 3.98 V on a rising supply. |
| 4 | PWM | input | PWM speed input on the A4949 (VSP on the A4945), with logic high of 2 V to 5.5 V, logic low of 0 to 0.8 V, an absolute maximum of -0.3 to 6 V, an internal 100 kΩ pulldown, and a PWM frequency range of 0.1 to 100 kHz. |
| 5 | VREF | power_in | Analog reference output at 3.2 to 3.4 V that requires a 0.1 µF X5R 10 V ceramic capacitor (CVREF) as stated in the application circuit. |
| 6 | FG | output | Open-drain speed output signal that changes state once per electrical motor revolution, with a 14 V maximum voltage, 10 mA maximum current, and 0.3 V maximum saturation voltage at 5 mA. |
| 7 | OUTC | output | Motor phase C terminal driven by the sinusoidal gate drive, with total driver RDS(on) of 1.1 Ω typical at VBB = 12 V and overcurrent limiting (IOCL) of 1.4 to 1.8 A. |
| 8 | OUTB | output | Motor phase B terminal driven by the sinusoidal gate drive, with total driver RDS(on) of 1.1 Ω typical at VBB = 12 V and overcurrent limiting (IOCL) of 1.4 to 1.8 A. |
| 9 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-8-EP |
| Category | Motor Driver ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Recommended supply voltage VBB (G version valid range) | VBB | 4 | 18 | V | G version; electrical characteristics header | 4 | |
| Supply Voltage | VBB | 18 | V | 2 | |||
| Input Logic Voltage Range | VIN | -0.3 | 6 | V | PWM and VSP pins | 2 | |
| Logic Output (FG pin) | VFG | 14 | V | FG pin | 2 | ||
| Logic Output Current (FG pin) | IFG | 10 | mA | FG pin | 2 | ||
| Operating Ambient Temperature | TA | -40 | 105 | °C | G temperature range | 2 | |
| Maximum Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature | Tstg | -55 | 150 | °C | 2 | ||
| VBB Supply Current | IBB | 10 | 15 | mA | VIN = 3 V | 4 | |
| Total Driver RDS(on) (Sink + Source) | RDS(on) | 1.1 | 1.4 | Ω | IOUT = 1 A, TJ = 25°C, VBB = 12 V | 4 | |
| Total Driver RDS(on) (Sink + Source) | RDS(on) | 1.5 | 1.8 | Ω | IOUT = 1 A, TJ = 25°C, VBB = 4 V | 4 | |
| Reference Voltage (VREF pin) | VREF | 3.2 | 3.3 | 3.4 | V | IFG = 5 mA | 4 |
| Output Saturation Voltage (FG Pin) | VFG(sat) | 0.3 | V | IFG = 5 mA | 4 | ||
| FG Output Leakage | IFG(LKG) | 1 | µA | VFG = 14 V | 4 | ||
| Motor PWM Frequency | fOUTPWM | 28 | 30 | 32 | kHz | 4 | |
| Input Current | IIN | 21 | 33 | 45 | µA | VIN = 3 V (RIN = 100 kΩ pulldown) | 4 |
| Logic Input (Low Level) | VIL | 0 | 0.8 | V | 4 | ||
| Logic Input (High Level) | VIH | 2 | 5.5 | V | 4 | ||
| Logic Input Hysteresis | VIHYS | 200 | 300 | 600 | mV | 4 | |
| PWM On Threshold | DON | 9.5 | 10 | 10.5 | % | 4 | |
| PWM Off Threshold | DOFF | 7 | 7.5 | 8 | % | 4 | |
| PWM Input Frequency Range | fPWM | 0.1 | 100 | kHz | 4 | ||
| VBB Undervoltage Lockout (UVLO) | VBBUVLO | 3.85 | 3.98 | V | VBB rising | 4 | |
| VBB UVLO Hysteresis | VBBUVHYS | 150 | 300 | 450 | mV | 4 | |
| Lock Protection | tOFF | 7 | 8 | 9 | s | 4 | |
| Overcurrent Limiting (OCL) | IOCL | 1.4 | 1.6 | 1.8 | A | 4 | |
| Thermal Shutdown Temperature (TSD) | TJTSD | 150 | 165 | 180 | °C | Temperature rising | 4 |
| Package Thermal Resistance (LJ package, 2-sided PCB, 0.8 in2 copper each side) | RθJA | 62 | °C/W | LJ package, 2-sided PCB with 0.8 in2 copper each side | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | for wave solder applications. Both packages are lead (Pb) free with 100% matte-tin leadframe plating. | 1 |
CAD (KiCad official)
- Symbol:
A4949GLJTR-T - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
a4949gljtr-t-etched.step/a4949gljtr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a4949gljtr-t.step/a4949gljtr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (12 pp, sha256
4b7c7efcaf5bd8b1, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).