A4919GETTR-T from Allegro MicroSystems, LLC, in a QFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBRG	input	Sense input to the top of the external MOSFET bridge for measuring high-side drain voltage; absolute maximum rating is -5 to 55 V with respect to GND.
2	GND	power_in	Analog reference, digital and power ground that must be connected to the supply ground; absolute maximum rating is -0.3 to 7 V.
3	VDDM	input	Logic supply monitor input on the no-LDO variant that must be connected to the system logic supply; an unlatched fault is set below VDDUV (2.7 V typ) and gate drives are disabled below VGDD (1.5 V typ), with a 60 kΩ typical internal pull-down; absolute maximum rating is -0.3 to 7 V.
4	VDSTH	input	Drain-source fault threshold programming input in which VDS fault reporting is disabled if driven below VDSD; absolute maximum rating is -0.3 to 6.5 V.
5	FAULT	output	Open-drain active-high programmable diagnostic output that may be pulled up by an external resistor to a maximum of 5.5 V; absolute maximum rating is -0.3 to 6.5 V.
6	AHI	input	Logic input that commands the phase A high-side gate drive to activate when logic high; absolute maximum rating is -0.3 to 6.5 V.
7	ALO	input	Logic input that commands the phase A low-side gate drive to activate when logic high; absolute maximum rating is -0.3 to 6.5 V.
8	BHI	input	Logic input that commands the phase B high-side gate drive to activate when logic high; absolute maximum rating is -0.3 to 6.5 V.
9	BLO	input	Logic input that commands the phase B low-side gate drive to activate when logic high; absolute maximum rating is -0.3 to 6.5 V.
10	CHI	input	Logic input that commands the phase C high-side gate drive to activate when logic high; absolute maximum rating is -0.3 to 6.5 V.
11	CLO	input	Logic input that commands the phase C low-side gate drive to activate when logic high; absolute maximum rating is -0.3 to 6.5 V.
12	LSS	passive	Low-side return path for discharging low-side MOSFET gate capacitance, connected to the common low-side sources through a low-impedance trace; absolute maximum rating is -4 to 6.5 V.
13	GLC	output	Low-side gate-drive output for the phase C external N-channel MOSFET; absolute maximum rating is -5 to 16 V.
14	GHC	output	High-side gate-drive output for the phase C external N-channel MOSFET; absolute maximum rating is Sx to Sx+15 V.
15	SC	passive	Motor connection for phase C that senses the switched voltage and serves as the negative supply for the floating high-side driver; absolute maximum rating is -5 to 55 V.
16	CC	passive	Bootstrap capacitor connection for phase C that supplies the high-side driver; absolute maximum rating is -0.3 to Sx + 15 V.
17	GLB	output	Low-side gate-drive output for the phase B external N-channel MOSFET; absolute maximum rating is -5 to 16 V.
18	GHB	output	High-side gate-drive output for the phase B external N-channel MOSFET; absolute maximum rating is Sx to Sx+15 V.
19	SB	passive	Motor connection for phase B that senses the switched voltage and serves as the negative supply for the floating high-side driver; absolute maximum rating is -5 to 55 V.
20	CB	passive	Bootstrap capacitor connection for phase B that supplies the high-side driver; absolute maximum rating is -0.3 to Sx + 15 V.
21	GLA	output	Low-side gate-drive output for the phase A external N-channel MOSFET; absolute maximum rating is -5 to 16 V.
22	GHA	output	High-side gate-drive output for the phase A external N-channel MOSFET; absolute maximum rating is Sx to Sx+15 V.
23	SA	passive	Motor connection for phase A that senses the switched voltage and serves as the negative supply for the floating high-side driver; absolute maximum rating is -5 to 55 V.
24	CA	passive	Bootstrap capacitor connection for phase A that supplies the high-side driver; absolute maximum rating is -0.3 to Sx + 15 V.
25	VREG	power_out	Regulated gate-drive supply output nominally 13 V that needs a sufficiently large storage capacitor; absolute maximum rating is -0.3 to 16 V.
26	CP2	passive	Charge-pump capacitor connection, with a minimum 220 nF (typically 470 nF) capacitor between CP1 and CP2; absolute maximum rating is -0.3 to 16 V.
27	CP1	passive	Charge-pump capacitor connection, with a minimum 220 nF (typically 470 nF) capacitor between CP1 and CP2; absolute maximum rating is -0.3 to 16 V.
28	VBB	power_in	Main power supply for all device functions, specified from 7 to 50 V and functional down to 5.5 V; absolute maximum rating is -0.3 to 50 V.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	QFN-28-EP(5x5)
Category	Power Management ICs
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VBB Functional Operating Range	VBB	5.5		50	V	Correct function, parameters not guaranteed	7
VBB Quiescent Current	IBBQ		10	14	mA	Operational mode, outputs low, VBB = 12 V	7
VBB Quiescent Current (Sleep mode)	IBBS			15	µA	Sleep mode, VBB = 12 V (A4919x, No LDO, variant)	7
VREG Output Voltage	VREG	12.5	13	13.75	V	VBB > 9 V, IREG = 0 to 15 mA	7
VREG Output Voltage	VREG	12	13	13.75	V	7.5 V < VBB ≤ 9 V, IREG = 0 to 10 mA	7
VREG Output Voltage	VREG	8.5	9.5		V	5.5 V < VBB ≤ 6 V, IREG < 8 mA	7
Bootstrap Diode Forward Voltage	VfBOOT	0.4	0.7	1	V	ID = 10 mA	7
Bootstrap Diode Forward Voltage	VfBOOT	1.5	2.2	3.1	V	ID = 100 mA	7
Bootstrap Diode Resistance	rD	6	13	28	Ω	rD(100mA) = (VfBOOT(150mA), VfBOOT(50mA)) / 100 (mA)	7
Bootstrap Diode Current Limit	IDBOOT	250	500	750	mA		7
Turn-Off Propagation Delay	tP(off)	60	90	180	ns	Input change to unloaded gate output change	7
Turn-On Propagation Delay	tP(on)	60	90	180	ns	Input change to unloaded gate output change	7
Pull-Up On Resistance	RDS(on)UP	5	8	13	Ω	TJ = 25°C, IGHx = -150 mA	7
Pull-Down On Resistance	RDS(on)DN	1.5	2.4	4.6	Ω	TJ = 25°C, IGLx = 150 mA	7
Input Low Voltage	VIL			0.8	V		8
Input High Voltage	VIH	2			V		8
Input Hysteresis	VIhys	100	300		mV		8
VDS Disable Voltage	VDSD			100	mV		8
Fault Disable Voltage	VFLTD			0.5	V		8
Output Low Voltage (FAULT)	VOL		0.2	0.4	V	IOL = 1 mA, no fault indicated	8
Output Leakage (FAULT)	IO	-1		1	µA	0 V < VO < 5.5 V, fault indicated	8
VREG Undervoltage Lockout (rising)	VREGON	7.5	8	8.5	V	VREG rising	8
VREG Undervoltage Lockout (falling)	VREGOFF	6.75	7.25	7.75	V	VREG falling	8
Bootstrap Undervoltage Threshold	VBOOTUV	62		75	%VREG	VBOOT falling, VCx, VSx	8
VDDM / V3 / V5 Undervoltage Threshold	VDDUV	2.45	2.7	2.85	V	Voltage falling	8
VDDM / V3 / V5 Undervoltage Hysteresis	VDDUVHys	40	100	160	mV		8
VDS Threshold, Internal	VDSTHI	1	1.2	1.4	V	VDSTH > 2.7 V	8
VDS Threshold Range	VDSTH	0.2		2	V		8
VDS Threshold Input Leakage	VDSTHL	-3		3	µA	0 V < VDSTH < 5.5 V	8
VBRG Input Current	IVBRG			250	µA	VDSTH = 2 V, VBB = 12 V, 0 V < VBRG < VBB	8
Short-to-Ground Threshold Offset	VSTGO	-100		100	mV	VDSTH ≥ 1 V	8
Short-to-Ground Threshold Offset	VSTGO	-150		150	mV	VDSTH < 1 V	8
Short-to-Power Supply Threshold Offset	VSTPO	-100		100	mV	VDSTH ≥ 1 V	8
Short-to-Power Supply Threshold Offset	VSTPO	-150		150	mV	VDSTH < 1 V	8
VDS Fault Blank Time	tBL	1.5	2.3	4.5	µs		8
Overtemperature Warning	TJF	170		180	°C	Temperature increasing	8
Input Low Voltage For Sleep Mode	VILS			0.5	V	xHI, xLO	8
Sleep Mode Activation Timeout	tSLT	7.5	10	12.5	ms	From all xHI, xLO < VIL	8
Wake-up from Sleep Delay	tWK			1	ms	Any xHI, xLO > VIH, CREG < 1 µF	8
Logic Monitor or Supply (VDDM, no-LDO variant)	VDDM, V3, V5	-0.3		7	V	with respect to GND	2
Load Supply Voltage	VBB	-0.3		50	V	with respect to GND	2
Terminal VREG	VREG	-0.3		16	V	with respect to GND	2
Terminals CP1, CP2	CP1, CP2	-0.3		16	V	with respect to GND	2
Logic Inputs	AHI, ALO, BHI, BLO, CHI, CLO	-0.3		6.5	V	with respect to GND	2
Terminal VBRG	VBRG	-5		55	V	with respect to GND	2
Terminal LSS	LSS	-4		6.5	V	with respect to GND	2
Terminals SA, SB, SC	SA, SB, SC	-5		55	V	with respect to GND	2
Terminals GLA, GLB, GLC	GLA, GLB, GLC	-5		16	V	with respect to GND	2
Terminals CA, CB, CC	CA, CB, CC	-0.3			V	with respect to GND	2
Terminal FAULT	FAULT	-0.3		6.5	V	with respect to GND	2
Terminal VDSTH	VDSTH	-0.3		6.5	V	with respect to GND	2
Ambient Operating Temperature Range	TA	-40		105	°C	Limited by power dissipation	2
Maximum Continuous Junction Temperature	TJ(max)			165	°C		2
Transient Junction Temperature	TtJ			175	°C	Overtemperature event not exceeding 10 seconds; lifetime duration not exceeding 10 hours	2
Storage Temperature Range	Tstg	-55		150	°C		2
Bootstrap Undervoltage Hysteresis	VBOOTHys		9		%VREG		8
Overtemperature Hysteresis	TJHyst		15		°C	Recovery = TJF, TJHyst	8
Gate Drive Disable Threshold	VGDD		1.5		V		8
Package Thermal Resistance (Junction to Ambient)	RθJA		32		°C/W	ET package, on 4-layer PCB based on JEDEC standard	2
Package Thermal Resistance (Junction to Pad)	RθJP		2		°C/W	ET package	2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	pad. Both packages are lead (Pb) free, with 100% matte-tin leadframe plating (suffix T).	1

CAD (KiCad official)

Symbol: A4919GETTR-T
Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
3D model: QFN-28-EP(5x5) (KiCad packages3D, STEP)
3D model files: a4919gettr-t-etched.step / a4919gettr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4919gettr-t.step / a4919gettr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (22 pp, sha256 c5982931c39e745c, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A4919GETTR-T

Verified A4919GETTR-T

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3D Model

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