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A4919GETTR-5-T

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Allegro MicroSystems, LLC Gate Drive ICs, QFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsa4919gettr-5-tfactory-2.0.0extractor-text

Verified A4919GETTR-5-T

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 29 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: A4919GETTR-5-T · QFN-28-EP(5x5) · 29 pins
  • ✓copper: 29 copper pads, none touching another net
  • ✓datasheet: all 29 pin names found in the 22-page datasheet
  • ✓distributor: lcsc C2677010, digikey 620-1977-2-ND, mouser 250-A4919GETTR-5-T
  • ✓family: QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-illru_4b/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.21)
  • ✓pads: 29 pins = 29 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 29 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ a4919gettr-5-t.kicad_sym✓ a4919gettr-5-t.kicad_mod✓ a4919gettr-5-t.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers a4919gettr-5-t: viewers · Ray 3d ago
a4919gettr-5-t-etched.glb Publish 0.1.0 · Ray 3d ago
a4919gettr-5-t-etched.step a4919gettr-5-t: factory component page (tier=lcsc) · Ray 3d ago
a4919gettr-5-t-hero.glb a4919gettr-5-t: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
a4919gettr-5-t-hero.overlay.json Publish 0.1.0 · Ray 3d ago
a4919gettr-5-t.glb Publish 0.1.0 · Ray 3d ago
a4919gettr-5-t.kicad_mod Publish 0.1.0 · Ray 3d ago
a4919gettr-5-t.kicad_sym Publish 0.1.0 · Ray 3d ago
a4919gettr-5-t.lbr Publish 0.1.0 · Ray 3d ago
a4919gettr-5-t.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier lcsc, 29 pins · Ray 3d ago

A4919GETTR-5-T

Allegro MicroSystems, LLC · Gate Drive ICs · QFN-28-EP(5x5)

A4919GETTR-5-T from Allegro MicroSystems, LLC, in a QFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBRG input Sense input to the top of the external MOSFET bridge that allows accurate measurement of the voltage at the drains of the high-side MOSFETs.
2 GND power_in Analog reference, digital, and power ground, to be connected to supply ground.
3 V5 power_out 5 V LDO regulator output for external circuitry only, with IV5 < 70 mA at VBB > 6 V, 5 mA < IV5 < 25 mA giving 4.9 to 5.2 V, an overcurrent limit of 130 to 260 mA, and at least 1 µF with ESR of no more than 250 mΩ fitted to GND.
4 VDSTH input Drain-source fault threshold programming pin where an external analog voltage sets the VDS fault threshold, reporting is disabled if driven below VDSD, and the internal value VDSTHI is used if driven above its analog input range.
5 FAULT output Open-drain active-high programmable diagnostic output that may be pulled up by an external resistor to a maximum of 5.5 V.
6 AHI input Logic input for the phase A high-side gate drive, where a logic high commands the high-side gate drive to be activated.
7 ALO input Logic input for the phase A low-side gate drive, where a logic high commands the low-side gate drive to be activated.
8 BHI input Logic input for the phase B high-side gate drive, where a logic high commands the high-side gate drive to be activated.
9 BLO input Logic input for the phase B low-side gate drive, where a logic high commands the low-side gate drive to be activated.
10 CHI input Logic input for the phase C high-side gate drive, where a logic high commands the high-side gate drive to be activated.
11 CLO input Logic input for the phase C low-side gate drive, where a logic high commands the low-side gate drive to be activated.
12 LSS passive Low-side return path for discharging the MOSFET gate capacitance, connected to the common sources of the low-side MOSFETs through a low-impedance PCB trace.
13 GLC output Low-side gate-drive output for the phase C external N-channel MOSFET.
14 GHC output High-side gate-drive output for the phase C external N-channel MOSFET.
15 SC passive Phase C motor connection that senses the switched load voltage and forms the negative supply for the floating high-side driver.
16 CC passive Phase C bootstrap capacitor connection and positive supply for the phase C high-side gate driver.
17 GLB output Low-side gate-drive output for the phase B external N-channel MOSFET.
18 GHB output High-side gate-drive output for the phase B external N-channel MOSFET.
19 SB passive Phase B motor connection that senses the switched load voltage and forms the negative supply for the floating high-side driver.
20 CB passive Phase B bootstrap capacitor connection and positive supply for the phase B high-side gate driver.
21 GLA output Low-side gate-drive output for the phase A external N-channel MOSFET.
22 GHA output High-side gate-drive output for the phase A external N-channel MOSFET.
23 SA passive Phase A motor connection that senses the switched load voltage and forms the negative supply for the floating high-side driver.
24 CA passive Phase A bootstrap capacitor connection and positive supply for the phase A high-side gate driver.
25 VREG power_out Regulated gate-drive supply, nominally 13 V, that powers the low-side drivers and charges the bootstrap capacitors and requires a sufficiently large storage capacitor.
26 CP2 passive Charge-pump capacitor connection, requiring a minimum 220 nF capacitor (typically 470 nF) between CP1 and CP2.
27 CP1 passive Charge-pump capacitor connection, requiring a minimum 220 nF capacitor (typically 470 nF) between CP1 and CP2.
28 VBB power_in Main power supply for all device functions, specified from 7 to 50 V and functional down to 5.5 V with reduced gate drive, with absolute maximum rating of −0.3 to 50 V.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package QFN-28-EP(5x5)
Category Power Management ICs
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage VBB -0.3 50 V With respect to GND 2
Logic Monitor or Supply VDDM, V3, V5 -0.3 7 V V3 or V5 with LDO regulator present; VDDM without LDO 2
Terminal VREG VREG -0.3 16 V 2
Terminals CP1, CP2 CP1, CP2 -0.3 16 V 2
Logic Inputs AHI, ALO, BHI, BLO, CHI, CLO -0.3 6.5 V 2
Terminal VBRG VBRG -5 55 V 2
Terminal LSS LSS -4 6.5 V 2
Terminals SA, SB, SC SA, SB, SC -5 55 V 2
Terminals GLA, GLB, GLC GLA, GLB, GLC -5 16 V 2
Terminal FAULT FAULT -0.3 6.5 V 2
Terminal VDSTH VDSTH -0.3 6.5 V 2
Ambient Operating Temperature Range TA -40 105 °C Limited by power dissipation 2
Maximum Continuous Junction Temperature TJ(max) 165 °C 2
Transient Junction Temperature TtJ 175 °C Overtemperature event not exceeding 10 seconds, lifetime not exceeding 10 hours 2
Storage Temperature Range Tstg -55 150 °C 2
VBB Functional Operating Range VBB 5.5 50 V Correct function, parameters not guaranteed 7
VBB Quiescent Current IBBQ 10 14 mA Operational mode, outputs low, VBB = 12 V 7
VREG Output Voltage VREG 12.5 13 13.75 V VBB > 9 V, IREG = 0 to 15 mA 7
VREG Output Voltage VREG 12 13 13.75 V 7.5 V < VBB ≤ 9 V, IREG = 0 to 10 mA 7
VREG Output Voltage VREG 8.5 9.5 V 5.5 V < VBB ≤ 6 V, IREG < 8 mA 7
Bootstrap Diode Forward Voltage VfBOOT 0.4 0.7 1 V ID = 10 mA 7
Bootstrap Diode Forward Voltage VfBOOT 1.5 2.2 3.1 V ID = 100 mA 7
Bootstrap Diode Resistance rD 6 13 28 Ω rD(100mA) = (VfBOOT(150mA), VfBOOT(50mA)) / 100 (mA) 7
Bootstrap Diode Current Limit IDBOOT 250 500 750 mA 7
Pull-Up On Resistance RDS(on)UP 5 8 13 Ω TJ = 25°C, IGHx = -150 mA 7
Pull-Down On Resistance RDS(on)DN 1.5 2.4 4.6 Ω TJ = 25°C, IGLx = 150 mA 7
Turn-Off Propagation Delay tP(off) 60 90 180 ns Input change to unloaded gate output change 7
Turn-On Propagation Delay tP(on) 60 90 180 ns Input change to unloaded gate output change 7
Input Low Voltage VIL 0.8 V 8
Input High Voltage VIH 2 V 8
Input Hysteresis VIhys 100 300 mV 8
VDS Disable Voltage VDSD 100 mV 8
Fault Disable Voltage VFLTD 0.5 V 8
Output Low Voltage (FAULT) VOL 0.2 0.4 V IOL = 1 mA, no fault indicated 8
Output Leakage (FAULT) IO -1 1 µA 0 V < VO < 5.5 V, fault indicated 8
VREG Undervoltage Lockout rising VREGON 7.5 8 8.5 V VREG rising 8
VREG Undervoltage Lockout falling VREGOFF 6.75 7.25 7.75 V VREG falling 8
Bootstrap Undervoltage Threshold VBOOTUV 62 75 %VREG VBOOT falling, VCx, VSx 8
VDDM / V3 / V5 Undervoltage Threshold VDDUV 2.45 2.7 2.85 V Voltage falling 8
VDDM / V3 / V5 Undervoltage Hysteresis VDDUVHys 40 100 160 mV 8
VDS Threshold, Internal VDSTHI 1 1.2 1.4 V VDSTH > 2.7 V 8
VDS Threshold Range VDSTH 0.2 2 V 8
VDS Threshold Input Leakage VDSTHL -3 3 µA 0 V < VDSTH < 5.5 V 8
VBRG Input Current IVBRG 250 µA VDSTH = 2 V, VBB = 12 V, 0 V < VBRG < VBB 8
Short-to-Ground Threshold Offset VSTGO -100 100 mV VDSTH ≥ 1 V 8
Short-to-Ground Threshold Offset VSTGO -150 150 mV VDSTH < 1 V 8
Short-to-Power Supply Threshold Offset VSTPO -100 100 mV VDSTH ≥ 1 V 8
Short-to-Power Supply Threshold Offset VSTPO -150 150 mV VDSTH < 1 V 8
VDS Fault Blank Time tBL 1.5 2.3 4.5 µs 8
Overtemperature Warning TJF 170 180 °C Temperature increasing 8
V5 Output Voltage V5 4.85 5.25 V IV5 < 70 mA, VBB > 6 V 9
V5 Output Voltage V5 4.9 5 5.2 V 5 mA < IV5 < 25 mA 9
V5 Output Overcurrent Limit ILDOOC(V5) 130 260 mA 9
V5 Shutdown Voltage Threshold VLDOSD(V5) 450 850 mV Voltage falling 9
V5 Shutdown Voltage Hysteresis VLDOHys(V5) 80 200 mV 9
Thermal Resistance Junction to Ambient (ET package, 4-layer PCB JEDEC) RθJA 32 °C/W ET package, on 4-layer PCB based on JEDEC standard 2
Thermal Resistance Junction to Pad (ET package) RθJP 2 °C/W ET package 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin pad. Both packages are lead (Pb) free, with 100% matte-tin leadframe plating (suffix T). 1

CAD (KiCad official)

  • Symbol: A4919GETTR-5-T
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: QFN-28-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: a4919gettr-5-t-etched.step / a4919gettr-5-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a4919gettr-5-t.step / a4919gettr-5-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (22 pp, sha256 c5982931c39e745c, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF