component
A4490EESTR-T
Public Made by Adomby adom
Allegro MicroSystems LLC Charge Pumps, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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A4490EESTR-T
Allegro MicroSystems LLC · Charge Pumps · QFN-20-EP(4x4)
A4490EESTR-T from Allegro MicroSystems LLC, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB1 | input | Feedback input for REG1, connected to the resistor divider from the VREG1 output (0.8 V target reference). |
| 2 | VDD | power_in | Bias supply for logic; externally supplied range is 3.3 to 5.5 V, recommended from a 3.3 to 5 V regulated output. |
| 3 | GND | power_in | Ground; should be connected externally to PGND. |
| 4 | FB2 | input | Feedback input for REG2, connected to the resistor divider from the VREG2 output. |
| 5 | ENB2 | input | Enable input for REG2, logic input, active high (VIH 2.0 V min, VIL 0.8 V max; input current limited to 1 mA). |
| 6 | LX2 | passive | Switch node for REG2, connected to the inductor and flyback diode. |
| 7 | VBB2 | power_in | Input supply for REG2; must be connected together externally with the other VBBx pins (4.5 to 34 V). |
| 8 | CPOR | passive | Power-on-reset delay adjustment; capacitor to ground sets tPOR = 2.131×10^5 × CPOR. |
| 9 | PORZ | output | Power-on-reset open-drain output, active low (VPORZL max 0.4 V at 1 mA). |
| 10 | VCP | passive | Charge pump reservoir capacitor connection. |
| 11 | CP2 | passive | Charge pump capacitor terminal. |
| 12 | CP1 | passive | Charge pump capacitor terminal. |
| 13 | PGND | power_in | Ground for charge pump circuitry; should be connected externally to GND and to the thermal vias. |
| 14 | FB3 | input | Feedback input for REG3, connected to the resistor divider from the VREG3 output. |
| 15 | ENB3 | input | Enable input for REG3, logic input, active high (VIH 2.0 V min, VIL 0.8 V max; input current limited to 1 mA). |
| 16 | LX3 | passive | Switch node for REG3, connected to the inductor and flyback diode. |
| 17 | VBB3 | power_in | Input supply for REG3; must be connected together externally with the other VBBx pins (4.5 to 34 V). |
| 18 | VBB1 | power_in | Input supply for REG1; must be connected together externally with the other VBBx pins (4.5 to 34 V). |
| 19 | LX1 | passive | Switch node for REG1, connected to the inductor and flyback diode. |
| 20 | ENB1 | input | Enable input for REG1, logic input, active high (VIH 2.0 V min, VIL 0.8 V max; input current limited to 1 mA). |
| 21 | PAD | power_in | Exposed pad for enhanced thermal dissipation; connect to the ground (0 V) plane using thermal vias. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | QFN-20-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage (absolute maximum) | VBB | 36 | V | 2 | |||
| LX1, LX2, and LX3 Pins (absolute maximum) | VLXn | -1 | 36 | V | 2 | ||
| PORZ and VDD Pins (absolute maximum) | VIN | -0.3 | 7 | V | 2 | ||
| ENBx Pin Input Current (absolute maximum) | IENBx | 1 | mA | Driven by a current-limited voltage source | 2 | ||
| Operating Ambient Temperature Range E (absolute maximum) | TA | -40 | 85 | ºC | 2 | ||
| Maximum Junction Temperature (absolute maximum) | TJ(max) | 150 | ºC | 2 | |||
| Storage Temperature (absolute maximum) | Tstg | -55 | 150 | ºC | 2 | ||
| Load Supply Voltage (recommended) | VBB | 4.5 | 34 | V | To operate at VBB < 6 V, connect VDD supply to the VBB supply | 2 | |
| LX1, LX2, and LX3 Pins (recommended) | VLXn | -0.7 | 34 | V | 2 | ||
| Operating Ambient Temperature (recommended) | TA | -40 | 85 | ºC | 2 | ||
| Junction Temperature (recommended) | TJ | -40 | 125 | ºC | 2 | ||
| Package Thermal Resistance | RθJA | 37 | ºC/W | On 4-layer PCB based on JEDEC standard | 2 | ||
| VBB Quiescent Current | IBBON | 1 | 2 | mA | ENBx = high, ILOAD = 0 mA, VBB = 12 V, current drawn by feedback resistors ignored | 5 | |
| VDD Supply Range | VDD | 3.3 | 5.5 | V | 5 | ||
| VDD Quiescent Current (ENBx high) | IDD | 6 | mA | ENBx = high | 5 | ||
| Feedback Input Bias Current | IBIAS | -400 | -100 | 100 | nA | 5 | |
| Feedback Voltage | VFB | -1.5 | 1.5 | % | With respect to 0.8 V target voltage | 5 | |
| Output Voltage Regulation | VOUT | -2.5 | 2.5 | % | VREGx = 5 V, IOUT = 0 to 1.5 A, TA = -20°C to 85°C | 5 | |
| Output Voltage Regulation | VOUT | -3.5 | 3.5 | % | VREGx = 5 V, IOUT = 0 to 1.5 A, TA = -40°C to 85°C | 5 | |
| PWM Frequency | fSW | 470 | 550 | 630 | kHz | 5 | |
| Maximum Duty Cycle | Dmax | 90 | % | 5 | |||
| Current Limit Threshold | ILIM | 2 | A | Peak current through switch with D = 0.9 | 5 | ||
| Soft Start Duration | tss | 0.625 | 1.25 | 1.875 | ms | 5 | |
| ENBx Input Voltage Low | VIL | 0.8 | V | 5 | |||
| ENBx Input Voltage High | VIH | 2 | V | 5 | |||
| ENBx Input Hysteresis | VI(hys) | 300 | 500 | mV | 5 | ||
| ENBx Input Current | IIL | -1 | 1 | μA | VIH ≤ 5 V | 5 | |
| PORZ Output Low Voltage | VPORZL | 0.4 | V | IPORZL = 1 mA, fault asserted | 5 | ||
| PORZ Output Leakage Current | IPORZH | -1 | 1 | μA | VPORZ = 5 V, fault not asserted | 5 | |
| Power-On Reset Duration | tPOR | 75 | 115 | 155 | ms | CPOR = 470 nF | 5 |
| VBB Undervoltage Lockout Startup (no external VDD) | VBBUV(su) | 3.7 | 4.3 | 4.7 | V | No external VDD supply, VBB rising | 6 |
| VBB Undervoltage Lockout Startup (external VDD) | VBBCPUV(su) | 3.8 | 4.2 | 4.6 | V | External VDD supply, VBB rising | 6 |
| VBB Undervoltage Lockout Shutdown (no external VDD) | VBBUV(sd) | 3.6 | 4.1 | 4.7 | V | No external VDD supply, VBB falling | 6 |
| VBB Undervoltage Lockout Shutdown (external VDD) | VBBCPUV(sd) | 3 | 3.5 | 4.3 | V | External VDD supply, VBB falling | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. | 2 |
CAD (KiCad official)
- Symbol:
A4490EESTR-T - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
a4490eestr-t-etched.step/a4490eestr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a4490eestr-t.step/a4490eestr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (17 pp, sha256
df57216978689102, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).