# A4481KLJTR-T

**Allegro MicroSystems, LLC** · Linear Voltage Regulators (LDO) · SOIC-8-EP

A4481KLJTR-T from Allegro MicroSystems, LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage pin for the regulator, operating from 5.25 V to 40 V with a 50 V load dump rating. |
| 2 | VIN | power_in | Input voltage pin for the regulator, operating from 5.25 V to 40 V with a 50 V load dump rating. |
| 3 | NC | unconnected | No connect pin. |
| 4 | ENB | input | Logic enable input from a microcontroller or DSP that must be above 2 V to operate, and is rated to 50 V so it can be connected directly to VIN. |
| 5 | POK | output | Open-drain regulator fault detection output that requires an external pull-up resistor and is pulled low when ENB goes low, UVLO occurs, TSD occurs, or UV/OVP occurs. |
| 6 | GND | power_in | Ground pin. |
| 7 | GND | power_in | Ground pin. |
| 8 | VOUT | power_out | 5 V ±1% regulator output capable of supplying up to 50 mA of load current. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8-EP |
| Category | Power Management |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN, ENB pin voltage | VIN, VENB | -0.3 |  | 50 | V |  | 2 |
| VOUT pin voltage | VOUT | -0.3 |  | 32 | V | Independent of VIN | 2 |
| All other pins voltage |  | -0.3 |  | 7 | V |  | 2 |
| Junction Temperature Range | TJ(max) | -40 |  | 165 | °C |  | 2 |
| Storage Temperature Range | Tstg | -40 |  | 150 | °C |  | 2 |
| Operating Temperature Range | TA | -40 |  | 150 | °C | Selection guide, K temperature range | 2 |
| Package Thermal Resistance (Junction to Ambient) | RθJA |  | 35 |  | °C/W | eSOIC-8 (LJ) package | 2 |
| Operating Input Voltage | VIN | 5.25 | 5.35 | 40 | V | ENB high | 4 |
| VIN UVLO Start Voltage | VIN(START) | 4.75 |  | 5.2 | V | VIN rising, ENB high | 4 |
| VIN UVLO Stop Voltage | VIN(STOP) | 4.55 |  | 5 | V | VIN falling, ENB high | 4 |
| VIN UVLO Hysteresis | VIN(HYS) |  | 0.2 |  | V | VIN(START), VIN(STOP) | 4 |
| Input Quiescent Current | IQ |  | 3.4 |  | mA | VIN = 5.25 V, ENB high | 4 |
| Input Sleep Supply Current | IQ(SLEEP) |  | 1 | 10 | µA | VIN = 5.25 V, ENB low | 4 |
| Output Voltage Accuracy | VOUT | 4.95 | 5 | 5.05 | V | IOUT = 25 mA, VIN = 5.25 V | 4 |
| Load Regulation |  | -1 |  | 1 | % | 5 mA < IOUT < 50 mA, VIN = 5.25 V | 4 |
| Output Capacitance Range | COUT | 3 | 4.7 | 10 | µF |  | 4 |
| Startup Time | tSTART | 0.7 | 1.5 | 2.3 | ms | COUT ≤ 4.7 µF, Load = 100 Ω ±5% (50 mA) | 4 |
| ENB Threshold rising | VENB(H) |  |  | 2 | V | VENB rising | 4 |
| ENB Threshold falling | VENB(L) | 0.8 |  |  | V | VENB falling | 4 |
| ENB Resistance | RENB |  | 100 |  | kΩ |  | 4 |
| ENB Filter/Deglitch Time | td(EN,FILT) | 10 | 15 | 25 | µs |  | 4 |
| Current Limit | ILIM | -55 | -80 | -140 | mA | VOUT = 5 V | 4 |
| Foldback Current | IFBK | -13 | -23 | -35 | mA | VOUT = 0 V | 4 |
| Thermal Shutdown Threshold | TTSD | 165 |  |  | °C | TJ rising | 4 |
| Thermal Shutdown Hysteresis | THYS |  | 15 |  | °C |  | 4 |
| VOUT OV Threshold rising | VOV(H) | 5.15 | 5.33 | 5.5 | V | VOUT rising | 4 |
| VOUT OV Threshold falling | VOV(L) |  | 5.3 |  | V | VOUT falling | 4 |
| VOUT OV Hysteresis | VOV(HYS) | 15 | 30 | 50 | mV | VOV(H), VOV(L) | 4 |
| VOUT UV Threshold rising | VUV(H) |  | 4.71 |  | V | VOUT rising | 4 |
| VOUT UV Threshold falling | VUV(L) | 4.5 | 4.68 | 4.85 | V | VOUT falling | 4 |
| VOUT UV Hysteresis | VUV(HYS) | 15 | 30 | 50 | mV | VUV(H), VUV(L) | 4 |
| VOUT Output Disconnect Threshold | VDISC |  | 7.2 |  | V | VOUT rising | 4 |
| POK Output Low Voltage | VPOK(L) |  | 150 | 400 | mV | ENB high, VIN ≥ 5.25 V, IPOK = 4 mA | 4 |
| POK Leakage Current | IPOK(LKG) |  |  | 2 | µA | VPOK = 3.3 V | 4 |
| OV and UV Filter/Deglitch Times | td(FILT) | 10 | 15 | 20 | µs | Applies to undervoltage of the VOUT voltages | 4 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte-tin leadframe plating. | 1 |

## CAD (KiCad official)

- Symbol: `A4481KLJTR-T`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `a4481kljtr-t-etched.step` / `a4481kljtr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a4481kljtr-t.step` / `a4481kljtr-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a4481kljtr-t-datasheet.pdf) (10 pp, sha256 `5264745c8eb6db5f`, retrieved 2026-11-02, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a4481kljtr-t-datasheet.pdf)