component
A4447SLJTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA4447SLJTR-T
Allegro MicroSystems, LLC · DC-DC Converters · SOIC-8-EP
A4447SLJTR-T from Allegro MicroSystems, LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Gate drive boost node, connected to the LX node through an external bootstrap capacitor (CBOOT 0.01 µF in the typical application). |
| 2 | ENB | input | On/off control logic input: pulled low (below 1.0 V) to enable the output and start soft start, open circuit (2.0 to 7 V) disables the switcher. |
| 3 | TSET | passive | Off-time setting pin: a resistor to ground sets the fixed off-time, with RTSET not smaller than 7.65 kΩ ±2%. |
| 4 | GND | power_in | Ground. |
| 5 | FB | input | Feedback input for the adjustable regulator, regulated to 0.8 V (±2%) from the output resistor divider. |
| 6 | VBIAS | power_in | Bias supply input, connected to VOUT when the VOUT target is between 3.3 and 5 V (absolute maximum 7 V), otherwise left open or fed from an external source. |
| 7 | LX | output | Buck switching node connecting to the external inductor and catch diode. |
| 8 | VIN | power_in | Supply input, 8 to 50 V operating range with 50 V absolute maximum. |
| 9 | PAD | passive | Exposed thermal pad on the bottom, to be soldered to a ground copper area with thermal vias for heat dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | SOIC-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Supply Voltage | VIN | 50 | V | 2 | |||
| VBIAS Input Voltage | VBIAS | -0.3 | 7 | V | 2 | ||
| SW Switching Voltage | VS | -1 | V | 2 | |||
| ENB Input Voltage Range | VENB | -0.3 | 7 | V | 2 | ||
| Operating Ambient Temperature Range | TA | -20 | 85 | °C | 2 | ||
| Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature | Tstg | -55 | 150 | °C | 2 | ||
| Package Thermal Resistance (Junction to Ambient) | RθJA | 35 | ºC/W | On 4-layer PCB based on JEDEC standard | 2 | ||
| Package Thermal Resistance (Junction to Ambient) | RθJA | 62 | ºC/W | On 2-layer generic test PCB with 0.8 in.2 of copper area each side | 2 | ||
| Package Thermal Resistance (Junction to Pad) | RθJP | 2 | ºC/W | 2 | |||
| VIN Quiescent Current | IVIN(Q) | 0.9 | 1.35 | mA | VENB = LOW, IOUT = 0 mA, VIN = 42 V, VBIAS = VOUT | 4 | |
| VIN Quiescent Current | IVIN(Q) | 4.4 | 6.35 | mA | VENB = LOW, IOUT = 0 mA, VIN = 42 V, VBIAS < 3 V | 4 | |
| VIN Quiescent Current | IVIN(Q) | 100 | µA | VENB = HIGH | 4 | ||
| VBIAS Input Current | IBIAS | 3.5 | 5 | mA | VBIAS = VOUT | 4 | |
| Fixed Off-Time Proportion | toff | -15 | 15 | % | Based on calculated value | 4 | |
| Feedback Voltage | VFB | 0.784 | 0.8 | 0.816 | V | 4 | |
| Output Voltage Regulation | VOUT | -3 | 3 | % | IOUT = 0 mA to 2 A | 4 | |
| Feedback Input Bias Current | IFB | -400 | -100 | 100 | nA | 4 | |
| Soft Start Time | tss | 5 | 10 | 15 | ms | 4 | |
| Buck Switch Current Limit | ICL | 2.2 | 3 | A | VFB > 0.4 V | 4 | |
| Buck Switch Current Limit | ICL | 0.5 | 1.2 | A | VFB < 0.4 V | 4 | |
| ENB Open Circuit Voltage | VOC | 2 | 7 | V | Output disabled | 4 | |
| ENB Input Voltage Threshold | VENB(0) | 1 | V | LOW level input (Logic 0), output enabled | 4 | ||
| ENB Input Current | IENB(0) | -10 | -1 | µA | VENB = 0 V | 4 | |
| VIN Undervoltage Threshold | VUVLO | 6.6 | 6.9 | 7.2 | V | VIN rising | 4 |
| VIN Undervoltage Hysteresis | VUVLO(hys) | 0.7 | 1.1 | V | VIN falling | 4 | |
| Buck Switch On Resistance | RDS(on) | 450 | mΩ | TA = 25°C, IOUT = 2 A | 4 | ||
| Buck Switch On Resistance | RDS(on) | 650 | mΩ | TA = 125°C, IOUT = 2 A | 4 | ||
| Thermal Shutdown Temperature | TJTSD | 165 | °C | Temperature increasing | 4 | ||
| Thermal Shutdown Hysteresis | TJTSD(hys) | 15 | °C | Recovery = TJTSD, TJTSD(hys) | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | the VOUT node to be located as close as practical to the A4447 (U1). Thermal conduction from the A4447 is enhanced by direct contact of its exposed thermal pad to the smaller ground area under the A44 | 9 |
CAD (KiCad official)
- Symbol:
A4447SLJTR-T - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
a4447sljtr-t-etched.step/a4447sljtr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a4447sljtr-t.step/a4447sljtr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (12 pp, sha256
16a3d24d2c6d99ee, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).