component
A4405KLPTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Linear Voltage Regulators (LDO), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA4405KLPTR-T
Allegro MicroSystems, LLC · Linear Voltage Regulators (LDO) · TSSOP-20
A4405KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage with a 5.5 to 36 V operating range and a 50 V absolute maximum for surges. |
| 2 | GND | power_in | Ground terminal. |
| 3 | TON | input | Buck regulator on-time programming pin, characterized with RTON = 412 kΩ. |
| 4 | ENBAT | input | Ignition enable input from the key or switch via a 1 kΩ series resistor, with VIGN(H) of 4.0 V maximum and VIGN(L) of 2.2 V minimum. |
| 5 | ENB | input | Logic enable input from the microcontroller, with VENB(H) of 2.0 V maximum and VENB(L) of 0.8 V minimum. |
| 6 | ENBATS | output | Open-drain ignition status output, with VENBATS(L) of 400 mV maximum at 4 mA. |
| 7 | NPOR | output | Active-low, open-drain fault indication output, with a low level of 400 mV maximum at 4 mA in the specified enable states. |
| 8 | CPOR | passive | NPOR delay programming pin, with a charge current of about −13 µA and a rising threshold of 1.0 to 1.4 V. |
| 9 | V5 | power_out | 5 V regulator output, accurate to 4.9 to 5.1 V for a 10 to 215 mA load when VVREG is at least 5.25 V. |
| 10 | V5P | power_out | 5 V tracking, short-to-battery protected regulator output, accurate to 4.9 to 5.1 V for a 10 to 270 mA load; protection diodes are required when driving a long harness or trace. |
| 11 | V33 | power_out | 3.3 V regulator output, accurate to 3.23 to 3.37 V for a 10 to 500 mA load. |
| 12 | G33 | output | Gate driver to the external MOSFET for 3.3 V regulation, with a maximum gate voltage of 9 to 15 V when VV33 is 3.0 V. |
| 13 | CLV33 | input | 3.3 V current sense and limit input, with a V33 overcurrent threshold of 175 to 245 mV between VREG and CLV33. |
| 14 | VREG | power_out | Buck regulator DC output at 5.25 to 5.60 V, also serving as the input to the 3.3 V external regulator. |
| 15 | ISEN- | input | Buck negative current sense pin at the sense resistor and diode node, with a VISEN threshold of 175 to 265 mV. |
| 16 | ISEN+ | input | Buck positive current sense pin at the sense resistor and ground node. |
| 17 | LX | output | Buck regulator switching node. |
| 18 | CP1 | passive | Charge pump capacitor terminal 1. |
| 19 | CP2 | passive | Charge pump capacitor terminal 2. |
| 20 | VCP | power_out | Charge pump reservoir capacitor terminal, with VVCP specified at 4.1 to 6.6 V above VIN. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-20 |
| Category | Power Supply Chip |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Pin | VIN | -0.3 | 50 | V | 2 | ||
| LX Pin | VLX | -0.3 | 50 | V | 2 | ||
| LX Pin transient | VLX | -1.5 | V | t < 250 ns | 2 | ||
| VCP, CP1, and CP2 Pins | VVCP, VCPx | -0.3 | 60 | V | 2 | ||
| ISEN- Pin | VISEN- | -0.5 | 1 | V | 2 | ||
| ISEN+ Pin | VISEN+ | -0.5 | 0.5 | V | 2 | ||
| ENBAT Pin | VENBAT | -0.3 | V | 2 | |||
| ENBAT Pin Current | IENBAT | -50 | 50 | mA | 2 | ||
| VREG Pin | VVREG | -0.3 | 8 | V | 2 | ||
| V33 Pin | VV33 | -0.3 | 7 | V | 2 | ||
| G33 Pin | VG33 | -0.3 | V | 2 | |||
| CLV33 Pin | VCLV33 | -0.3 | 10 | V | 2 | ||
| V5P Pin | VV5P | -0.3 | V | 2 | |||
| V5 Pin | VV5 | -0.3 | 7 | V | 2 | ||
| TON Pin | VTON | -0.3 | 50 | V | 2 | ||
| NPOR and CPOR Pins | VxPOR | -0.3 | 7 | V | 2 | ||
| ENB and ENBATS Pins | VEN, VENBATS | -0.3 | 7 | V | 2 | ||
| Operating Ambient Temperature, range K | TA | -40 | 135 | °C | 2 | ||
| Junction Temperature | TJ(max) | -40 | 150 | °C | 2 | ||
| Storage Temperature Range | Tstg | -40 | 150 | °C | 2 | ||
| Package Thermal Resistance | RθJA | 32 | ºC/W | Estimated on 4-layer PCB based on JEDEC standard | 2 | ||
| Operating Input Voltage | VIN(op) | 5.5 | 13.5 | 36 | V | 6 | |
| Function Input Voltage | VIN(f) | 5.5 | 46 | V | Device functional, parameters not guaranteed | 6 | |
| Supply Quiescent Current (sleep) | IQ(SLEEP) | 10 | µA | VIN = 13.5 V, VIGN < VIGN(L), VENB < VENB(L), no load on VREG | 6 | ||
| Switcher Output | VVREG | 5.25 | 5.45 | 5.6 | V | ENB = high, VINSW(L) < VIN < 27 V, 25 mA < IVREG < 600 mA | 6 |
| Switcher Output | VVREG | 5.3 | 5.45 | 5.6 | V | ENB = high, VINSW(NOM) < VIN < 27 V, 25 mA < IVREG <750 mA | 6 |
| Switcher Output | VVREG | 5.15 | 6.46 | V | ENB = high, 5.5 V < VIN < 6.5 V, LX 100% on, 100 mA < IVREG < 600 mA | 6 | |
| Switcher On-Time | tON | 1070 | 1335 | 1600 | ns | VIN = 7 V, RTON = 412 kΩ | 6 |
| Switcher On-Time | tON | 160 | 200 | 240 | ns | VIN = 13.5 V, RTON = 412 kΩ | 6 |
| Switcher On-Time | tON | 80 | 118 | 135 | ns | VIN = 27 V, RTON = 412 kΩ | 6 |
| Switcher On-Time | tON | 220 | 275 | 330 | ns | VIN = 35 V, RTON = 412 kΩ | 6 |
| Switcher Period VIN Threshold | VINSW(L) | 5.9 | 6.2 | 6.5 | V | VIN falling, TSW changes from TSW(L) to 100% duty cycle | 6 |
| Switcher Period VIN Threshold | VINSW(NOM) | 7.7 | 8.3 | 8.9 | V | VIN falling, TSW changes from TSW(NOM) to TSW(L) | 6 |
| Switcher Period VIN Threshold | VINSW(H) | 28 | 31 | 34 | V | VIN rising, TSW changes from TSW(NOM) to TSW(H) | 6 |
| Buck Switch On-Resistance | RDS(on) | 275 | 300 | mΩ | TJ = 25°C, IDS = 0.1 A | 6 | |
| Buck Switch On-Resistance | RDS(on) | 400 | 470 | mΩ | TJ = 150°C, IDS = 0.1 A | 6 | |
| Minimum On-time | ton(min) | 65 | 90 | ns | VIN = 13.5 V, RTON = 49.9 kΩ | 6 | |
| Minimum Off-time | toff(min) | 85 | 110 | 140 | ns | VIN = 13.5 V | 6 |
| ISEN Voltage Threshold | VISEN | 175 | 220 | 265 | mV | VISEN+, VISEN- | 6 |
| VREG Peak Current Limit | ILIM(PEAK) | 2.5 | 5 | A | 6 | ||
| V5 Accuracy and Load Regulation | VV5 | 4.9 | 5 | 5.1 | V | 10 mA < IV5 < 215 mA, VVREG ≥ 5.25 V | 7 |
| V5P Accuracy and Load Regulation | VV5P | 4.9 | 5 | 5.1 | V | 10 mA < IV5P < 270 mA, VVREG ≥ 5.25 V | 7 |
| V5P/V33 Tracking Accuracy | ErrV5Ptrack | -0.5 | 0.5 | % | 2.69 V < VV33 < 3.37 V, IV5P = 75 mA, 5.5 V < VIN < 27 V | 7 | |
| V33 Accuracy | ErrV33 | 3.23 | 3.3 | 3.37 | V | 10 mA < IV33 < 500 mA | 7 |
| G33 Source Current | IG33(SRC) | -175 | -250 | -400 | µA | VV33 = 3.0 V, VG33 = VG33(MAX), 1 V | 7 |
| G33 Sink Current | IG33(SINK) | 0.5 | 3 | mA | VV33 = 3.6 V, VG33 = 6 V | 7 | |
| G33 Maximum Voltage | VG33(MAX) | 9 | 15 | V | VV33 = 3.0 V | 7 | |
| G33 Minimum Voltage | VG33(MIN) | 0.7 | 1 | V | VV33 = 3.6 V | 7 | |
| External FET Gate Capacitance | CISS | 250 | 5200 | pF | 7 | ||
| Charge Pump Output Voltage | ΔVVCP | 4.1 | 6.6 | V | VVCP − VIN | 7 | |
| ENB Logic Input Threshold (high) | VENB(H) | 2 | V | VENB rising | 7 | ||
| ENB Logic Input Threshold (low) | VENB(L) | 0.8 | V | VENB falling | 7 | ||
| ENB Logic Input Current | IENB(IN) | 100 | µA | VENB = 3.3 V | 7 | ||
| ENBAT and ENBATS Thresholds (high) | VIGN(H) | 4 | V | VIGN rising via a 1 kΩ series resistance, measure VIGN when IQ occurs | 7 | ||
| ENBAT and ENBATS Thresholds (low) | VIGN(L) | 2.2 | V | VIGN falling via a 1 kΩ series resistance, measure VIGN when IQ(SLEEP) occurs | 7 | ||
| ENBAT Input Current | IENBAT(IN) | 50 | 100 | µA | VIGN = 5.5 V via a 1 kΩ series resistance | 7 | |
| ENBAT Input Current | IENBAT(IN) | 0.5 | 5 | µA | VIGN = 0.8 V via a 1 kΩ series resistance | 7 | |
| ENBATS Output Voltage | VENBATS(L) | 400 | mV | IENBATS = 4 mA | 7 | ||
| NPOR Output Voltage | VNPOR(L) | 400 | mV | ENB = high or ENBAT = high, VVREG < VREGNPOR(L) or VV33 < V33NPOR(L), INPOR ≤ 4 mA | 8 | ||
| Thermal Shutdown Threshold | TJTSD | 155 | 170 | ºC | TJ rising | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | package with exposed thermal pad (suffix LP). The package is lead (Pb) free with 100% matte-tin leadframe plating | 2 |
CAD (KiCad official)
- Symbol:
A4405KLPTR-T - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
a4405klptr-t-etched.step/a4405klptr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a4405klptr-t.step/a4405klptr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (27 pp, sha256
ac41eeb6d8c7b5ac, retrieved 2026-10-29, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).