component
A4402KLPTR-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Linear Voltage Regulators (LDO), HTSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA4402KLPTR-T
Allegro MicroSystems, LLC · Linear Voltage Regulators (LDO) · HTSSOP-16
A4402KLPTR-T from Allegro MicroSystems, LLC, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TON | input | On-time setting terminal; a resistor from TON to VIN1 sets the buck converter on-time for a given input voltage. |
| 2 | GND | power_in | Ground terminal. |
| 3 | FB2 | input | Feedback input for the linear regulator output VLIN, set by the R3/R4 divider. |
| 4 | VIN2 | power_in | Input voltage 2, which supplies the linear regulator and should be connected to the switcher output when VSW is between 3 and 5.5 V. |
| 5 | VO2 | power_out | Regulator 2 (linear regulator) output. |
| 6 | WDI | input | Watchdog input; if the watchdog is not used it should be pulled to ground through a 4.7 kΩ resistor. |
| 7 | TSET | passive | Soft start and watchdog timing capacitor terminal; the external capacitor on TSET sets both the soft start time and the WDI timing. |
| 8 | NPOR | output | Fault output; open-drain power-on reset output that is pulled low on a POR event. |
| 9 | FB1 | input | Feedback input for the switching regulator output VSW, set by the R1/R2 divider. |
| 10 | POR | passive | POR delay terminal; an external capacitor on POR sets the reset delay tPOR. |
| 11 | ISEN | input | Current sense input that sets the switcher current limit; connect to GND through a series sense resistor RSENSE. |
| 12 | BOOT | passive | Boot node for LX; a 0.01 µF X7R bootstrap capacitor rated at least 25 V connects between BOOT and LX. |
| 13 | LX | output | Switching regulator output (switch node) of the buck converter. |
| 14 | GND | power_in | Ground terminal. |
| 15 | VIN1 | power_in | Input voltage 1, the buck converter input, with supply range 6 to 50 V. |
| 16 | ENB | input | Enable input; active high enables the device, and when set low the device enters sleep mode drawing a maximum of 1 µA. |
| 17 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | HTSSOP-16 |
| Category | Power Supply Chip |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Quiescent Current (VENB = 5 V, IOUT = 0 mA) | IIN(Q) | 1 | 6 | mA | VENB = 5 V, IOUT = ISW + ILIN = 0 mA, 13.5 V < VIN1 < 50 V | 5 | |
| Supply Quiescent Current in sleep (ENB low) | IIN(Q) | 1 | µA | VENB = 0 V, 13.5 V < VIN1 < 18 V, IOUT = ISW + ILIN = 0 mA | 5 | ||
| ENB Logic Input Voltage (rising) | VENB | 2 | 2.28 | 2.56 | V | VENB rising | 5 |
| ENB Logic Input Current, high level | IENB | 100 | µA | High input level, VENB = 3 V | 5 | ||
| ENB Logic Input Current, low level | IENB | -2 | 2 | µA | Low input level, VENB < 0.4 V | 5 | |
| Feedback Voltage, linear regulator | VFB2 | 1.156 | 1.18 | 1.204 | V | 1 mA < IO2 < 250 mA, 3.3 V < VIN2 < 5 V | 5 |
| VO2 Undervoltage Lockout Threshold | VO2UVLO | 0.896 | 0.944 | 0.99 | V | VO2 rising based on FB voltage | 5 |
| VO2 Undervoltage Lockout Hysteresis | VO2UVHYS | 30 | 50 | 70 | mV | 5 | |
| Feedback Input Bias Current, linear regulator | IFB2 | -100 | 100 | 400 | nA | 5 | |
| Current Limit, linear regulator | IO2 | 250 | 350 | mA | 5 | ||
| Feedback Voltage, switching regulator | VFB1 | 1.139 | 1.18 | 1.221 | V | IOUT = ISW + ILIN = 1 mA to 1.0 A, 8 V < VIN1 < 18 V | 5 |
| Feedback Input Bias Current, switching regulator | IFB1 | -400 | -100 | 100 | nA | VIN1 = 6 V | 5 |
| Switcher On Time | ton | 450 | 640 | 830 | ns | VIN1 = 19.25 V, Rton = 750 kΩ | 5 |
| Switcher On Time | ton | 165 | 230 | 300 | ns | VIN1 = 13.5 V, Rton = 750 kΩ | 5 |
| Switcher On Time | ton | 1050 | 1480 | 1925 | ns | VIN1 = 8 V, Rton = 750 kΩ | 5 |
| ton Low Voltage Threshold | VPL | 8.1 | 9 | 9.9 | V | VIN1 rising | 5 |
| ton High Voltage Threshold | VPH | 15.75 | 17.5 | 19.25 | V | VIN1 rising | 5 |
| Minimum On-Time | tonmin | 80 | ns | 5 | |||
| Minimum Off-Time | toffmin | 130 | ns | 5 | |||
| ISEN Voltage | VISEN | -350 | -250 | -150 | mV | 5 | |
| Valley Current Limit Threshold | Ilim | 550 | mA | 6 V < VIN1 < 8 V | 5 | ||
| NPOR Output Voltage | VNPOR | 400 | mV | INPOR = 1 mA | 5 | ||
| NPOR Leakage Current | INPOR | 1.5 | µA | VNPOR = 5.5 V | 5 | ||
| NPOR Reset Voltage | VNPORRESET | 0.7 | V | 20 kΩ pullup connected to VOUT2 | 5 | ||
| TSET Current, Watchdog Mode | ITSETWDI | 7 | 10 | 14 | µA | NPOR = high | 6 |
| WDI Frequency | fWDI | 100 | kHz | 6 | |||
| WDI Duty Cycle | DCWDI | 10 | 90 | % | 6 | ||
| WDI Logic Input Current | IWDI | -20 | 20 | µA | VWDI = 0 to 5 V | 6 | |
| TSET Current, Soft Start Mode | ITSETSS | 14 | 20 | 26 | µA | NPOR = low | 6 |
| POR Current | IPOR | 3.92 | 5.6 | 7.28 | µA | 6 | |
| VIN1 Pin voltage | VIN1 | -0.3 | 50 | V | 2 | ||
| VIN2 Pin voltage | VIN2 | -0.3 | 7 | V | 2 | ||
| LX Pin voltage | VLX | -1 | 50 | V | 2 | ||
| ISEN Pin voltage | VISEN | -0.5 | 1 | V | 2 | ||
| ENB Pin voltage | VENB | -0.3 | 7 | V | 2 | ||
| VO2 Pin voltage | VO2 | -0.3 | 7 | V | 2 | ||
| WDI Pin voltage | VWDI | -0.3 | 6 | V | 2 | ||
| TON Pin voltage | VTON | -0.3 | 7 | V | 2 | ||
| FB1 and FB2 Pins voltage | VFBx | -0.3 | 7 | V | 2 | ||
| NPOR voltage | VNPOR | -0.3 | 6.5 | V | 2 | ||
| TSET Pin voltage | VTSET | -0.3 | 7 | V | 2 | ||
| POR Pin voltage | VPOR | -0.3 | 6 | V | 2 | ||
| Ambient Operating Temperature Range K | TA | -40 | 150 | °C | Range K | 2 | |
| Junction Temperature (max) | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature Range | Tstg | -40 | 150 | °C | 2 | ||
| Supply voltage range VIN1 | VIN1 | 6 | 50 | V | Valid for Temperature Range K version at TJ = -40°C to 150°C, unless otherwise noted | 5 | |
| Second supply range for VIN2 | VIN2 | 3 | 5.5 | V | Second supply used to power VIN2 when the switcher voltage is greater than 5 V | 9 | |
| Package thermal resistance, junction to ambient | RθJA | 34 | °C/W | On 4-layer PCB based on JEDEC standard JESD51-7 | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. | 1 |
CAD (KiCad official)
- Symbol:
A4402KLPTR-T - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
a4402klptr-t-etched.step/a4402klptr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a4402klptr-t.step/a4402klptr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (18 pp, sha256
3941d9412abe8197, retrieved 2026-10-24, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).