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A3988SEVTR-T

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Allegro MicroSystems, LLC Motor Driver ICs, QFN-36-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsa3988sevtr-tfactory-2.0.0extractor-text

Verified A3988SEVTR-T

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 37 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: A3988SEVTR-T · QFN-36-EP(6x6) · 37 pins
  • ✓copper: 37 copper pads, none touching another net
  • ✓datasheet: all 37 pin names found in the 14-page datasheet
  • ✓distributor: lcsc C163256, digikey 620-1176-2-ND, mouser 250-A3988SEVTR-T
  • ✓family: QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-s6tm3ezv/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.12)
  • ✓pads: 37 pins = 37 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 37 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ a3988sevtr-t.kicad_sym✓ a3988sevtr-t.kicad_mod✓ a3988sevtr-t.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers a3988sevtr-t: viewers · Ray 2d ago
a3988sevtr-t-etched.glb Publish 0.1.0 · Ray 2d ago
a3988sevtr-t-etched.step a3988sevtr-t: factory component page (tier=lcsc) · Ray 2d ago
a3988sevtr-t-hero.glb a3988sevtr-t: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
a3988sevtr-t-hero.overlay.json Publish 0.1.0 · Ray 2d ago
a3988sevtr-t.glb Publish 0.1.0 · Ray 2d ago
a3988sevtr-t.kicad_mod Publish 0.1.0 · Ray 2d ago
a3988sevtr-t.kicad_sym Publish 0.1.0 · Ray 2d ago
a3988sevtr-t.lbr Publish 0.1.0 · Ray 2d ago
a3988sevtr-t.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier lcsc, 37 pins · Ray 2d ago

A3988SEVTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · QFN-36-EP(6x6)

A3988SEVTR-T from Allegro MicroSystems, LLC, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I04 input Control input I0 for bridge 4, setting the current level with I14; logic levels are 0.7×VDD min high and 0.3×VDD max low.
2 OUT1A output DMOS full-bridge 1 output A, rated up to 1.2 A and 36 V.
3 SENSE1 passive Sense resistor terminal for bridge 1; voltage must not exceed ±500 mV.
4 OUT1B output DMOS full-bridge 1 output B, rated up to 1.2 A and 36 V.
5 VBB1 power_in Load supply voltage, 8.0 to 36 V operating; must be connected together with VBB2 close to the device.
6 OUT2B output DMOS full-bridge 2 output B, rated up to 1.2 A and 36 V.
7 SENSE2 passive Sense resistor terminal for bridge 2; voltage must not exceed ±500 mV.
8 OUT2A output DMOS full-bridge 2 output A, rated up to 1.2 A and 36 V.
9 PHASE4 input Control input setting the current direction of bridge 4.
10 PHASE3 input Control input setting the current direction of bridge 3.
11 VDD power_in Logic supply voltage, 3.0 to 5.5 V operating.
12 VREF1 input Analog reference input for bridge 1, 0.0 to 1.5 V operating, setting ITripMax = VREF/(3×RS).
13 VREF2 input Analog reference input for bridge 2, 0.0 to 1.5 V operating, setting ITripMax = VREF/(3×RS).
14 VREF3 input Analog reference input for bridge 3, 0.0 to 1.5 V operating, setting ITripMax = VREF/(3×RS).
15 VREF4 input Analog reference input for bridge 4, 0.0 to 1.5 V operating, setting ITripMax = VREF/(3×RS).
16 GND power_in Ground.
17 PHASE2 input Control input setting the current direction of bridge 2.
18 PHASE1 input Control input setting the current direction of bridge 1.
19 I14 input Control input I1 for bridge 4, setting the current level with I04.
20 OUT4A output DMOS full-bridge 4 output A, rated up to 1.2 A and 36 V.
21 SENSE4 passive Sense resistor terminal for bridge 4; voltage must not exceed ±500 mV.
22 OUT4B output DMOS full-bridge 4 output B, rated up to 1.2 A and 36 V.
23 VBB2 power_in Load supply voltage, 8.0 to 36 V operating; must be connected together with VBB1 close to the device.
24 OUT3B output DMOS full-bridge 3 output B, rated up to 1.2 A and 36 V.
25 SENSE3 passive Sense resistor terminal for bridge 3; voltage must not exceed ±500 mV.
26 OUT3A output DMOS full-bridge 3 output A, rated up to 1.2 A and 36 V.
27 I13 input Control input I1 for bridge 3, setting the current level with I03.
28 I12 input Control input I1 for bridge 2, setting the current level with I02.
29 I11 input Control input I1 for bridge 1, setting the current level with I01.
30 GND power_in Ground.
31 VCP passive Reservoir capacitor terminal; a 0.1 µF ceramic capacitor is required between VCP and VBBx.
32 CP1 passive Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
33 CP2 passive Charge pump capacitor terminal; a 0.1 µF ceramic capacitor is connected between CP1 and CP2.
34 I01 input Control input I0 for bridge 1, setting the current level with I11.
35 I02 input Control input I0 for bridge 2, setting the current level with I12.
36 I03 input Control input I0 for bridge 3, setting the current level with I13.
37 PAD passive Exposed pad for enhanced thermal performance; should be soldered to the PCB.

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package QFN-36-EP(6x6)
Category Power Management ICs
Pins 37

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage Range VBB 8 36 V Operating 5
Logic Supply Voltage Range VDD 3 5.5 V Operating 5
VDD Supply Current IDD 7 10 mA 5
Output On Resistance, Source driver RDS(on) 700 800 mΩ IOUT = -1.2 A, TJ = 25°C 5
Output On Resistance, Sink driver RDS(on) 700 800 mΩ IOUT = 1.2 A, TJ = 25°C 5
Vf, Outputs Vf 1.3 V IOUT = 1.2 A 5
Output Leakage IDSS -20 20 µA Outputs, VOUT = 0 to VBB 5
VBB Supply Current IBB 8 mA IOUT = 0 mA, outputs on, PWM = 50 kHz, DC = 50% 5
Logic Input Voltage high VIN(1) 0.7 V 0.7×VDD (min printed as 0.7×VDD) 5
Logic Input Voltage low VIN(0) 0.3 V 0.3×VDD (max printed as 0.3×VDD) 5
Logic Input Current IIN -20 1 20 µA VIN = 0 to 5 V; typ printed <1.0 5
Input Hysteresis Vhys 150 300 500 mV 5
Propagation Delay, PWM change to source on tpd 350 550 1000 ns PWM change to source on 5
Propagation Delay, PWM change to source off tpd 35 300 ns PWM change to source off 5
Propagation Delay, PWM change to sink on tpd 350 550 1000 ns PWM change to sink on 5
Propagation Delay, PWM change to sink off tpd 35 250 ns PWM change to sink off 5
Crossover Delay tCOD 300 425 1000 ns 5
Blank Time tBLANK 0.7 1 1.3 µs 5
VREFx Pin Input Voltage Range VREFx 0 1.5 V Operating 5
VREFx Pin Reference Input Current IREF 1 µA VREF = 1.5; printed ±1 5
Current Trip-Level Error, 100% VERR -5 5 % VREF = 1.5, phase current = 100% 5
Current Trip-Level Error, 67% VERR -5 5 % VREF = 1.5, phase current = 67% 5
Current Trip-Level Error, 33% VERR -15 15 % VREF = 1.5, phase current = 33% 5
VBB UVLO Threshold VUV(VBB) 7.3 7.6 7.9 V VBB rising 5
VBB Hysteresis VUV(VBB)hys 400 500 600 mV 5
VDD UVLO Threshold VUV(VDD) 2.65 2.8 2.95 V VDD rising 5
VDD Hysteresis VUV(VDD)hys 75 105 125 mV 5
Thermal Shutdown Temperature TJTSD 155 165 175 °C 5
Thermal Shutdown Hysteresis TJTSDhys 15 °C 5
Load Supply Voltage VBB -0.5 36 V 2
Load Supply Voltage, pulsed VBB 38 V Pulsed tw < 1 µs 2
Logic Supply Voltage VDD -0.4 7 V 2
Output Current IOUT 1.2 A Do not exceed specified current rating or junction temperature of 150°C 2
Output Current, pulsed IOUT 2.8 A Pulsed tw < 1 µs 2
Logic Input Voltage Range VIN -0.3 7 V 2
SENSEx Pin Voltage VSENSEx 0.5 V 2
SENSEx Pin Voltage, pulsed VSENSEx 2.5 V Pulsed tw < 1 µs 2
VREFx Pin Voltage VREFx 2.5 V 2
Operating Temperature Range TA -20 85 ºC Range S 2
Junction Temperature TJ(max) 150 ºC 2
Storage Temperature Range Tstg -40 125 ºC 2
Package Thermal Resistance RθJA 27 ºC/W EV package, 4 layer PCB based on JEDEC standard 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin package height of 0.90 mm. The JP is a 7 mm × 7 mm 48 pin LQFP. Both packages are lead (Pb) free, with 100% matte tin 1

CAD (KiCad official)

  • Symbol: A3988SEVTR-T
  • Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
  • 3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: a3988sevtr-t-etched.step / a3988sevtr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a3988sevtr-t.step / a3988sevtr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (14 pp, sha256 d98c46bb6e4ac606, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF