component

A3979SLPTR-T

Public Made by Adom

by adom

Allegro MicroSystems, LLC Motor Driver ICs, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsa3979slptr-tfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

A3979SLPTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · HTSSOP-28

A3979SLPTR-T from Allegro MicroSystems, LLC, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENSE1 passive Sense resistor connection for Bridge 1; voltage on this pin must not exceed the 0.5 V maximum rating.
2 HOME output Logic output indicating the translator is at its initial Home state; goes low on RESET (VHOME(1) ≥ 0.7×VDD at -200 µA, VHOME(0) ≤ 0.3×VDD at 200 µA).
3 DIR input Logic input setting the motor rotation direction; changes take effect on the next rising edge of STEP.
4 OUT1A output DMOS full-bridge output A for Bridge 1, rated up to 35 V and ±2.5 A.
5 PFD input Percent fast decay input: above 0.6×VDD selects Slow decay, below 0.21×VDD selects Fast decay, in between selects Mixed decay; decouple with 0.1 µF.
6 RC1 passive Analog RT/CT timing connection to ground setting the fixed off-time (tOFF = RT×CT) and blanking time (tBLANK = 1400×CT) for Bridge 1.
7 AGND power_in Analog ground; must be connected externally to PGND.
8 REF input Current trip reference voltage input (0 to VDD); ITRIPmax = VREF/8RS, and VREF should not exceed 4 V in other than full-step modes.
9 RC2 passive Analog RT/CT timing connection to ground setting the fixed off-time (tOFF = RT×CT) and blanking time (tBLANK = 1400×CT) for Bridge 2.
10 VDD power_in Logic supply, 3.0 to 5.5 V operating range (7.0 V absolute maximum).
11 OUT2A output DMOS full-bridge output A for Bridge 2, rated up to 35 V and ±2.5 A.
12 MS2 input Logic input that together with MS1 selects the microstep resolution (full, half, quarter, sixteenth); changes take effect on the next rising STEP edge.
13 MS1 input Logic input that together with MS2 selects the microstep resolution (full, half, quarter, sixteenth); changes take effect on the next rising STEP edge.
14 SENSE2 passive Sense resistor connection for Bridge 2; voltage on this pin must not exceed the 0.5 V maximum rating.
15 VBB2 power_in Load supply for Bridge 2, 8 to 35 V operating; decouple with an electrolytic capacitor (>47 µF recommended) close to the device.
16 SR input Logic input selecting synchronous rectification: low enables Active mode, high disables it.
17 RESET input Active-low logic input that sets the translator to the Home state and turns off all DMOS outputs; STEP inputs are ignored until it is high.
18 OUT2B output DMOS full-bridge output B for Bridge 2, rated up to 35 V and ±2.5 A.
19 STEP input Logic input where a low-to-high transition advances the motor one microstep (minimum pulse width 1 µs).
20 VREG passive Internally generated regulator voltage for the sink-side DMOS outputs; must be decoupled with a 0.22 µF capacitor to ground.
21 PGND power_in Power ground; must be connected externally to AGND.
22 VCP passive Charge pump reservoir capacitor connection; a 0.22 µF ceramic capacitor is required between VCP and VBB.
23 CP1 passive Charge pump capacitor terminal 1; connect a 0.22 µF ceramic capacitor between CP1 and CP2.
24 CP2 passive Charge pump capacitor terminal 2; connect a 0.22 µF ceramic capacitor between CP1 and CP2.
25 OUT1B output DMOS full-bridge output B for Bridge 1, rated up to 35 V and ±2.5 A.
26 ENABLE input Active-low logic input that enables the DMOS outputs; logic high disables the outputs while translator inputs remain active.
27 SLEEP input Active-low logic input for sleep mode to minimize power consumption; allow 1 ms after wake-up before issuing STEP.
28 VBB1 power_in Load supply for Bridge 1, 8 to 35 V operating; decouple with an electrolytic capacitor (>47 µF recommended) close to the device.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package HTSSOP-28
Category Power Management ICs
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage Range, operating VBB 8 35 V Operating 4
Load Supply Voltage Range, sleep VBB 0 35 V During Sleep mode 4
Output Leakage Current high IDSS 1 20 μA VOUT = VBB 4
Output Leakage Current low IDSS -20 1 μA VOUT = 0 V 4
Source driver On Resistance RDS(On) 0.28 0.335 Ω Source driver, IOUT = -2.5 A 4
Sink driver On Resistance RDS(On) 0.22 0.265 Ω Sink driver, IOUT = 2.5 A 4
Source Diode Forward Voltage VF 1.4 V Source diode, IF = -2.5 A 4
Sink Diode Forward Voltage VF 1.4 V Sink diode, IF = 2.5 A 4
Motor Supply Current IBB 8 mA fPWM < 50 kHz 4
Motor Supply Current, outputs disabled IBB 6 mA Operating, outputs disabled 4
Motor Supply Current, sleep IBB 20 μA Sleep mode 4
Logic Supply Voltage Range VDD 3 5 5.5 V Operating 4
Logic Supply Current IDD 12 mA fPWM < 50 kHz 4
Logic Supply Current, outputs off IDD 10 mA Outputs off 4
Logic Supply Current, sleep IDD 20 μA Sleep mode 4
Logic Input Voltage high VIN(1) 0.7 xVDD 4
Logic Input Voltage low VIN(0) 0.3 xVDD 4
Logic Input Current high IIN(1) -20 1 20 μA VIN = 0.7 × VDD 4
Logic Input Current low IIN(0) -20 1 20 μA VIN = 0.3 × VDD 4
Reference Input Voltage Range VREF 0 5.5 V Operating (0 to VDD) 4
Reference Input Current IREF 0 3 μA 4
HOME Output Voltage high VHOME(1) 0.7 xVDD IHOME(1) = -200 μA 4
HOME Output Voltage low VHOME(0) 0.3 xVDD IHOME(0) = 200 μA 4
Mixed Decay Trip Point high VPFDH 0.6 xVDD 4
Mixed Decay Trip Point low VPFDL 0.21 xVDD 4
Gain Error at 38.27% phase current EG -10 10 % VREF = 2 V, Phase Current = 38.27% 4
Gain Error at 70.71% phase current EG -5 5 % VREF = 2 V, Phase Current = 70.71% 4
Gain Error at 100% phase current EG -5 5 % VREF = 2 V, Phase Current = 100.00% 4
STEP Pulse Width tW 1 μs 4
Blank Time tBLANK 700 950 1200 ns RT = 56 kΩ, CT = 680 pF 4
Fixed Off-Time tOFF 30 38 46 μs RT = 56 kΩ, CT = 680 pF 4
Crossover Dead Time tDT 100 475 800 ns Synchronous rectification enabled 4
Thermal Shutdown Temperature TJSD 165 °C 5
Thermal Shutdown Hysteresis TJSDHYS 15 °C 5
UVLO Enable Threshold VUVLO 2.45 2.7 2.95 V Increasing VDD 5
UVLO Hysteresis VUVLOHYS 0.05 0.1 V 5
Data Set-Up Time A 200 ns Minimum command active time before step pulse; TA = +25°C, VDD = 5 V 6
Data Hold Time B 200 ns Minimum command active time after step pulse; TA = +25°C, VDD = 5 V 6
Minimum STEP Low Time D 1 μs TA = +25°C, VDD = 5 V 6
Maximum Wake-Up Time E 1 ms TA = +25°C, VDD = 5 V 6
Load Supply Voltage VBB 35 V 2
Output Current IOUT -2.5 2.5 A May be limited by duty cycle, ambient temperature, heat sinking; do not exceed junction temperature of 150°C 2
Logic Supply Voltage VDD 7 V 2
Logic Input Voltage Range, tW > 30 ns VIN -0.3 V tW > 30 ns; max VDD + 0.3 V 2
Logic Input Voltage Range, tW < 30 ns VIN -1 V tW < 30 ns; max VDD + 1 V 2
Sense Voltage VSENSE 0.5 V 2
Operating Ambient Temperature TA -20 85 °C Range S 2
Junction Temperature TJ(max) 150 °C 2
Storage Temperature Tstg -55 150 °C 2
Package Thermal Resistance, 2-layer PCB RθJA 32 ºC/W Two-layer PCB with 3.8 in.2 of copper area on each side connected with thermal vias and to device exposed pad 5
Package Thermal Resistance, High-K PCB RθJA 28 ºC/W High-K PCB (multilayer with significant copper areas, based on JEDEC standard) 5

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin 28-pin TSSOP with exposed thermal pad. The package is lead (Pb) free, with 100% matte tin leadframe plating. 1

CAD (KiCad official)

  • Symbol: A3979SLPTR-T
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28 (KiCad packages3D, STEP)
  • 3D model files: a3979slptr-t-etched.step / a3979slptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a3979slptr-t.step / a3979slptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (15 pp, sha256 914c40550526a032, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF