A3977SLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SENSE1	passive	Sense resistor connection for bridge 1; the SENSE terminal maximum rating is 0.5 V (DC).
2	HOME	output	Logic output indicating the translator's initial home state; it goes low during RESET and at home state.
3	DIR	input	Direction input that sets the direction of motor rotation.
4	OUT1A	output	DMOS H bridge 1 output A, rated for ±2.5 A and 35 V.
5	PFD	input	Mixed decay setting input; above 0.6 × VDD selects slow decay and below 0.21 × VDD selects fast decay, with a 0.1 µF decoupling capacitor recommended.
6	RC1	passive	Analog input for the fixed off-time timing network of bridge 1, connected to RT and CT to ground.
7	AGND	power_in	Analog ground that must be connected externally to PGND (pin 21) on the TSSOP package.
8	REF	input	Gm reference input; the reference voltage range is 0 to VDD and sets the current limit via ITRIPmax = VREF / 8 × RS.
9	RC2	passive	Analog input for the fixed off-time timing network of bridge 2, connected to RT and CT to ground.
10	VDD	power_in	Logic supply voltage, operating range 3.0 to 5.5 V.
11	OUT2A	output	DMOS H bridge 2 output A, rated for ±2.5 A and 35 V.
12	MS2	input	Logic input that selects the microstep resolution together with MS1 per Table 1.
13	MS1	input	Logic input that selects the microstep resolution together with MS2 per Table 1.
14	SENSE2	passive	Sense resistor connection for bridge 2; the SENSE terminal maximum rating is 0.5 V (DC).
15	VBB2	power_in	Load supply for bridge 2, operating range 8.0 to 35 V.
16	SR	input	Logic input that selects synchronous rectification: logic low enables active mode and logic high disables it.
17	RESET	input	Active-low logic input that sets the translator to the home state and turns off all DMOS outputs.
18	OUT2B	output	DMOS H bridge 2 output B, rated for ±2.5 A and 35 V.
19	STEP	input	Logic input where a low-to-high transition advances the motor one microstep increment; maximum STEP frequency is 500 kHz.
20	VREG	passive	Internally generated regulator voltage for the sink-side DMOS outputs, to be decoupled with a 0.22 µF capacitor to ground.
21	PGND	power_in	Power ground that must be connected externally to AGND (pin 7) on the TSSOP package.
22	VCP	passive	Charge pump reservoir capacitor node, requiring a 0.22 µF ceramic capacitor between VCP and VBB.
23	CP1	passive	Charge pump capacitor terminal, requiring a 0.22 µF ceramic capacitor between CP1 and CP2.
24	CP2	passive	Charge pump capacitor terminal, requiring a 0.22 µF ceramic capacitor between CP1 and CP2.
25	OUT1B	output	DMOS H bridge 1 output B, rated for ±2.5 A and 35 V.
26	ENABLE	input	Active-low logic input that enables all DMOS outputs; when logic high the outputs are disabled.
27	SLEEP	input	Active-low logic input that minimizes power consumption by disabling the output DMOS, regulator and charge pump; a 1 ms wake-up time applies.
28	VBB1	power_in	Load supply for bridge 1, operating range 8.0 to 35 V.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	TSSOP-28-EP
Category	Power Management ICs
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Load Supply Voltage	VBB			35	V		2
Logic Supply Voltage	VDD			7	V		2
Logic Input Voltage Range	VIN	-0.3			V	Pulsed, tw > 30 ns	2
Logic Input Voltage Range	VIN	-1			V	Pulsed, tw < 30 ns	2
Sense Voltage (DC)	VSENSE			0.5	V		2
Output Current	IOUT	-2.5		2.5	A		2
Operating Ambient Temperature Range S	TA	-20		85	°C	Range S	2
Maximum Junction Temperature	TJ(max)			150	°C		2
Storage Temperature	Tstg	-55		150	°C		2
Load Supply Voltage Range, Operating	VBB	8		35	V	Operating	6
Load Supply Voltage Range, During Sleep Mode	VBB	0		35	V	During sleep mode	6
Output Leakage Current	IDSS			20	µA	VOUT = VBB	6
Output Leakage Current	IDSS			-20	µA	VOUT = 0 V	6
Output On Resistance, Source Driver	RDS(on)		0.28	0.335	Ω	Source driver, IOUT = -2.5 A	6
Output On Resistance, Sink Driver	RDS(on)		0.22	0.265	Ω	Sink driver, IOUT = 2.5 A	6
Body Diode Forward Voltage, Source Diode	VF			1.4	V	Source diode, IF = -2.5 A	6
Body Diode Forward Voltage, Sink Diode	VF			1.4	V	Sink diode, IF = 2.5 A	6
Motor Supply Current	IBB			8	mA	fPWM < 50 kHz	6
Motor Supply Current	IBB			6	mA	Operating, outputs disabled	6
Motor Supply Current	IBB			20	µA	Sleep mode	6
Logic Supply Voltage Range	VDD	3	5	5.5	V	Operating	6
Logic Input Current, high	IIN(1)	-20		20	µA	VIN = 0.7 × VDD	6
Logic Input Current, low	IIN(0)	-20		20	µA	VIN = 0.3 × VDD	6
Maximum STEP Frequency	fSTEP	500			kHz		6
Blank Time	tBLANK	700	950	1200	ns	Rt = 56 kΩ, Ct = 680 pF	6
Fixed Off Time	toff	30	38	46	µs	Rt = 56 kΩ, Ct = 680 pF	6
Reference Input Voltage Range	VREF	0			V	Operating	6
Reference Input Current	IREF	-3	0	3	µA		6
Gain (gm) Error	EG	-10		10	%	VREF = 2 V, Phase Current = 38.27%	6
Gain (gm) Error	EG	-5		5	%	VREF = 2 V, Phase Current = 70.71%	6
Crossover Dead Time	tDT	100	475	800	ns	SR enabled	6
UVLO Enable Threshold	VUVLO	2.45	2.7	2.95	V	Increasing VDD	6
UVLO Hysteresis	ΔVUVLO	0.05	0.1		V		6
Logic Supply Current	IDD			12	mA	fPWM < 50 kHz	6
Logic Supply Current	IDD			10	mA	Outputs off	6
Logic Supply Current, Sleep Mode	IDD			20	µA	Sleep mode	6
Minimum Command Active Time Before Step Pulse (Data Setup Time)		200			ns	TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground	9
Minimum Command Active Time After Step Pulse (Data Hold Time)		200			ns	TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground	9
Minimum STEP Pulse Width		1			µs	TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground	9
Minimum STEP Low Time		1			µs	TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground	9
Maximum Wake-Up Time				1	ms	TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground	9
Package Thermal Resistance	RθJA		28		°C/W	Package LP, on 4-layer PCB based on JEDEC standard	2
Thermal Shutdown Temperature	TJ		165		°C		6
Thermal Shutdown Hysteresis	ΔTJ		15		°C		6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	an exposed thermal pad (suffix LP). The A3977 is lead (Pb) free, with 100% matte tin leadframe plating.	1

CAD (KiCad official)

Symbol: A3977SLPTR-T
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: TSSOP-28-EP (KiCad packages3D, STEP)
3D model files: a3977slptr-t-etched.step / a3977slptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a3977slptr-t.step / a3977slptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (17 pp, sha256 d5b5c7b7d14cbc27, retrieved 2026-11-05, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A3977SLPTR-T

Verified A3977SLPTR-T

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3D Model

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