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A3950SLPTR-T

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Allegro MicroSystems LLC Global Sourcing Parts, HTSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A3950SLPTR-T

Allegro MicroSystems LLC · Global Sourcing Parts · HTSSOP-16

A3950SLPTR-T from Allegro MicroSystems LLC, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NFAULT output Fault output that is open drain and is driven active low by a motor fault, undervoltage condition, or TJ > 160°C, with VOL of 0.4 V maximum at 1.0 mA sink.
2 MODE input Logic input that toggles between fast decay mode (low) and slow decay mode (high), with VIH of 2.0 V minimum and VIL of 0.8 V maximum.
3 PHASE input Logic input for direction control, with VIH of 2.0 V minimum and VIL of 0.8 V maximum; logic input voltages must not exceed 7 V.
4 GND power_in Ground pin; the exposed thermal pad is connected to the GND pins and the copper ground plane under the pad makes a good star ground point.
5 SLEEP input Logic input where a logic low puts the device into Sleep mode and a logic high allows normal operation, with VIH of 2.7 V minimum and VIL of 0.8 V maximum.
6 ENABLE input Logic input for enable/chop control, with VIH of 2.0 V minimum and VIL of 0.8 V maximum; logic input voltages must not exceed 7 V.
7 OUTA output DMOS full-bridge output A, rated for an output current of 2.8 A maximum (6 A transient for under 500 ns) and VBB to OUTx of 36 V maximum.
8 SENSE passive Power return pin for current sensing, where the voltage on SENSE must not exceed ±500 mV.
9 VBB power_in Load supply voltage, specified for operation from 8 V to 36 V with an absolute maximum of 36 V.
10 OUTB output DMOS full-bridge output B, rated for an output current of 2.8 A maximum (6 A transient for under 500 ns) and OUTx to SENSE of 36 V maximum.
11 CP1 passive Charge pump capacitor terminal; a 0.1 µF ceramic monolithic capacitor is connected between CP1 and CP2.
12 CP2 passive Charge pump capacitor terminal; a 0.1 µF ceramic monolithic capacitor is connected between CP1 and CP2.
13 GND power_in Ground pin; the exposed thermal pad is connected to the GND pins and the copper ground plane under the pad makes a good star ground point.
14 VCP passive Reservoir capacitor terminal; a 0.1 µF ceramic monolithic capacitor is connected between VCP and VBB, and VCP undervoltage disables the outputs.
15 VREG passive Regulator decoupling terminal that should be decoupled with a 0.22 µF capacitor to ground, and VREG undervoltage disables the outputs.
16 NC unconnected No connection.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems LLC
Package HTSSOP-16
Category Global Sourcing Parts
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage VBB 36 V 2
Output Current IOUT 2.8 A 2
Sense Voltage VSENSE -500 500 mV 2
VBB to OUTx VBB-OUTx 36 V 2
OUTx to SENSE OUTx-SENSE 36 V 2
Logic Input Voltage VIN -0.3 7 V 2
Operating Ambient Temperature TA -20 85 °C Range S 2
Maximum Junction Temperature TJ(max) 150 °C 2
Storage Temperature Tstg -40 125 °C 2
Transient Output Current IOUT 6 A TW < 500 ns 2
Motor Supply Current IBB 6 8.5 mA fPWM < 50 kHz 4
Motor Supply Current (charge pump on, outputs disabled) IBB 3 4.5 mA Charge pump on, outputs disabled 4
Motor Supply Current (sleep mode) IBB 10 µA Sleep mode 4
PHASE, ENABLE, MODE Input Voltage High VIH 2 V 4
PHASE, ENABLE, MODE Input Voltage Low VIL 0.8 V 4
SLEEP Input Voltage High VIH 2.7 V 4
SLEEP Input Voltage Low VIL 0.8 V 4
PHASE, MODE Input Current High IIH 20 µA VIN = 2.0 V 4
PHASE, MODE Input Current Low IIL -20 20 µA VIN = 0.8 V 4
ENABLE Input Current High IIH 40 100 µA VIN = 2.0 V 4
ENABLE Input Current Low IIL 16 40 µA VIN = 0.8 V 4
SLEEP Input Current High IIH 27 50 µA VIN = 2.7 V 4
SLEEP Input Current Low IIL 10 µA VIN = 0.8 V 4
NFAULT Output Voltage Low VOL 0.4 V Isink = 1.0 mA 4
Input Hysteresis, except SLEEP VIHys 100 150 250 mV 4
Output On Resistance, source driver 25°C RDS(on) 0.35 0.48 Ω Source driver, IOUT = -2.8 A, TJ=25°C 4
Output On Resistance, source driver 125°C RDS(on) 0.55 0.8 Ω Source driver, IOUT = -2.8 A, TJ=125°C 4
Output On Resistance, sink driver 25°C RDS(on) 0.3 0.43 Ω Sink driver, IOUT = 2.8 A, TJ=25°C 4
Output On Resistance, sink driver 125°C RDS(on) 0.45 0.7 Ω Sink driver, IOUT = 2.8 A, TJ=125°C 4
Body Diode Forward Voltage, source diode Vf 1.4 V Source diode, If = -2.8 A 4
Body Diode Forward Voltage, sink diode Vf 1.4 V Sink diode, If = 2.8 A 4
Overcurrent Threshold IOCP 3 A 4
Package Thermal Resistance, LP 4-layer PCB RθJA 34 ºC/W LP package, 4-layer PCB based on JEDEC standard 4
Package Thermal Resistance, LP 2-layer PCB RθJA 43 ºC/W LP package, 2-layer PCB with 3.8 in.2 copper both sides, connected by thermal vias 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin for enhanced thermal dissipation, and are lead (Pb) free with 100% matte tin leadframe plating. 1

CAD (KiCad official)

  • Symbol: A3950SLPTR-T
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: a3950slptr-t-etched.step / a3950slptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a3950slptr-t.step / a3950slptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems LLC datasheet (13 pp, sha256 75c87cb19da6863b, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF