A3944KLPTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · TSSOP-28-EP

A3944KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDR	power_in	Positive gate drive supply for the GATx outputs, with an absolute maximum rating of -0.3 to 6.5 V.
2	GAT0	output	Gate drive 0 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate.
3	DRN0	input	Gate drive 0 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults.
4	GAT1	output	Gate drive 1 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate.
5	DRN1	input	Gate drive 1 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults.
6	GAT2	output	Gate drive 2 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate.
7	DRN2	input	Gate drive 2 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults.
8	GAT3	output	Gate drive 3 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate.
9	DRN3	input	Gate drive 3 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults.
10	GAT4	output	Gate drive 4 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate.
11	DRN4	input	Gate drive 4 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults.
12	GAT5	output	Gate drive 5 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate.
13	DRN5	input	Gate drive 5 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults.
14	VREG	power_out	Regulated voltage output for analog and reference functions, with an absolute maximum rating of -0.3 to 20 V.
15	VBB	power_in	Analog battery supply for the voltage regulator, which can connect to battery through reverse polarity protection, with an absolute maximum rating of -0.3 to 40 V.
16	GND	power_in	Power ground return that connects to the common return point for all external MOSFET source connections.
17	IN5	input	Gate drive 5 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V.
18	IN4	input	Gate drive 4 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V.
19	IN3	input	Gate drive 3 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V.
20	IN2	input	Gate drive 2 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V.
21	IN1	input	Gate drive 1 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V.
22	IN0	input	Gate drive 0 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V.
23	CSN	input	Active-low serial interface chip select with pull-up resistor; data is latched into the serial register when CSN goes high, rated -0.3 to 6.5 V.
24	SI	input	Active-high serial data input with pull-down resistor, clocked into the serial register on the rising edge of SCK, rated -0.3 to 6.5 V.
25	SCK	input	Serial interface clock input with pull-down resistor, rated -0.3 to 6.5 V.
26	SO	output	Push-pull serial data output that carries fault register data on the falling edge of SCK and goes high impedance when CSN is high, rated -0.3 to 6.5 V.
27	RESETN	input	Active-low chip reset input that forces outputs low, resets the configuration and clears channel faults when held low longer than the minimum reset pulse width, rated -0.3 to 6.5 V.
28	VDD	power_in	Positive logic supply for digital inputs, outputs and logic, with an absolute maximum rating of -0.3 to 6.5 V.
29	PAD	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	TSSOP-28-EP
Category	Power Management ICs
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog Supply Voltage	VBB	-0.3		40	V	with respect to ground at TA = 25°C	2
Logic Supply Voltage	VDD	-0.3		6.5	V	with respect to ground at TA = 25°C	2
Gate Drive Supply Voltage	VDR	-0.3		6.5	V	with respect to ground at TA = 25°C	2
Terminal VREG	VREG	-0.3		20	V	with respect to ground at TA = 25°C	2
Terminals GATx	GATx	-0.3		6.5	V	with respect to ground at TA = 25°C	2
Terminals DRNx	DRNx	-0.3		50	V	with respect to ground at TA = 25°C	2
Terminals INx	INx	-0.3		6.5	V	with respect to ground at TA = 25°C	2
Terminals SI, SCK, CSN		-0.3		6.5	V	with respect to ground at TA = 25°C	2
Terminal SO	SO	-0.3		6.5	V	with respect to ground at TA = 25°C	2
Terminal RESETN	RESETN	-0.3		6.5	V	with respect to ground at TA = 25°C	2
Drain Feedback Clamp Energy	EDRNC			10	µJ	Single pulse less than 2 ms	2
Drain Feedback Clamp Current	IDRNC			100	mA	Single pulse not exceeding EDRN or PDRN	2
Drain Feedback Clamp Power	PDRNC			100	mW	Average power over any 2 ms period	2
Junction Temperature	TJ(max)			150	°C		2
Transient Junction Temperature	TtJ			175	°C	Overtemperature event not exceeding 10 s, lifetime duration not exceeding 10 hours	2
Storage Temperature Range	Tstg	-55		150	°C		2
Operating Temperature Range, Range K	TA	-40		150	°C	Range K	2
Logic Supply Voltage	VDD	3		5.5	V	Valid at TJ = -40°C to 150°C	6
Analog Supply Voltage	VBB	6		40	V	Valid at TJ = -40°C to 150°C	6
Gate Drive Supply Voltage	VDR	3		6	V	Valid at TJ = -40°C to 150°C	6
VDD Quiescent Current	IDDQ			3	mA		6
VBB Quiescent Current	IBBQ			4	mA		6
VBB Quiescent Current	IBBQ			10	µA	VDD = 0, VBB ≤ 30 V	6
VDR Quiescent Current	IDRQ			4	mA		6
Regulator Voltage	VREG	17.5		18.5	V	VBB > 19.5 V	6
Regulator Dropout	VDO	0		0.6	V		6
RESETN Pulse Width	tRST	1			µs		6
RESETN Glitch Filter	tRGF			200	ns		6
Oscillator Frequency	fOSC	1.4	2	2.6	MHz		6
Input High Voltage	VIH	70			%VDD		6
Input Low Voltage	VIL			30	%VDD		6
Input Hysteresis	VIhys	300	500		mV		6
SO Output Low Voltage	VOL		0.2	0.4	V	SO, IOL = 2 mA	6
SO Output Leakage	IL	-1		1	µA	CSN = VDD	6
Pull-Up On-Resistance	RDS(on)UP		50	70	Ω	TJ = 25°C, IGHx = -20 mA	6
Pull-Up On-Resistance	RDS(on)UP		75	125	Ω	TJ = 150°C, IGHx = -20 mA	6
Pull-Down On-Resistance	RDS(on)DN		50	95	Ω	TJ = 25°C, IGLx = 20 mA	6
Pull-Down On-Resistance	RDS(on)DN		75	145	Ω	TJ = 150°C, IGLx = 20 mA	6
Output Sink Current	IGL	20			mA	GATx off, VGATx = VDR	6
Output Source Current	IGH			-40	mA	GATx on, VGATx = 0 V	6
Minimum On-Time	ton			1	µs	At INx input	6
Minimum Off-Time	toff			1	µs	At INx input	6
RESETN to GATx			0.5	1	µs		6
Drain Clamp Voltage	VDCL	45			V	IDRNx = 10 µA	7
Drain Clamp Leakage	IDC			1	µA	VDRNx < 32 V	7
VDD Undervoltage Lockout	VDDUV	2.6	2.75	2.9	V	Decreasing VDD	8
VREG Undervoltage Lockout	VREGUV	4.5	4.8	5.1	V	Decreasing VREG	8
Overtemperature Warning Threshold	TJW	145	160	175	ºC	Temperature increasing	8
Short-to-Battery Threshold	VSTB	30	31	32	%VREG	GATx driven high, SB[2:0] = 111	7
Pull-Up Diagnostic Current	IDPU	-80	-65	-50	µA	GATx low, VDRNx < (VOCL, 200 mV)	7
Pull-Down Diagnostic Current	IDPD	50	65	80	µA	GATx low, NPD = 0, VDRNx >(VOCL + 200 mV)	7
Short-to-Ground Threshold	VSTG	65	66	67	%VREG	GATx driven low, SG = 1	7
Short-to-Ground Threshold	VSTG	44	45	46	%VREG	GATx driven low, SG = 0	7
Open-Load Threshold	VOL	75	76	77	%VREG	GATx driven low	7
Open-Load Clamp Voltage	VOCL	70	71	72	%VREG		7
Package Thermal Resistance, Junction to Ambient	RθJA		28		ºC/W	4-layer PCB based on JEDEC standard	2
Package Thermal Resistance, Junction to Ambient	RθJA		32		ºC/W	2-layer PCB with 3.8 in.2 of copper area each side	2
Package Thermal Resistance, Junction to Pad	RθJP		2		ºC/W		2
Drain Clamp Voltage	VDCL		54		V	IDRNx = 10 mA	7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	LP) with an exposed thermal pad. The package is lead (Pb) free with 100% matte-tin leadframe plating.	1

CAD (KiCad official)

Symbol: A3944KLPTR-T
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: TSSOP-28-EP (KiCad packages3D, STEP)
3D model files: a3944klptr-t-etched.step / a3944klptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a3944klptr-t.step / a3944klptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (31 pp, sha256 01679bb65c0b7218, retrieved 2026-10-28, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# A3944KLPTR-T

**Allegro MicroSystems, LLC** · Motor Driver ICs · TSSOP-28-EP

A3944KLPTR-T from Allegro MicroSystems, LLC, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDR | power_in | Positive gate drive supply for the GATx outputs, with an absolute maximum rating of -0.3 to 6.5 V. |
| 2 | GAT0 | output | Gate drive 0 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate. |
| 3 | DRN0 | input | Gate drive 0 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults. |
| 4 | GAT1 | output | Gate drive 1 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate. |
| 5 | DRN1 | input | Gate drive 1 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults. |
| 6 | GAT2 | output | Gate drive 2 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate. |
| 7 | DRN2 | input | Gate drive 2 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults. |
| 8 | GAT3 | output | Gate drive 3 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate. |
| 9 | DRN3 | input | Gate drive 3 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults. |
| 10 | GAT4 | output | Gate drive 4 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate. |
| 11 | DRN4 | input | Gate drive 4 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults. |
| 12 | GAT5 | output | Gate drive 5 output, driven between GND and VDR and connected directly or through a resistor to the external MOSFET gate. |
| 13 | DRN5 | input | Gate drive 5 drain sense analog high-voltage input, rated to 50 V, used to monitor the FET drain for short-to-battery, short-to-ground and open-load faults. |
| 14 | VREG | power_out | Regulated voltage output for analog and reference functions, with an absolute maximum rating of -0.3 to 20 V. |
| 15 | VBB | power_in | Analog battery supply for the voltage regulator, which can connect to battery through reverse polarity protection, with an absolute maximum rating of -0.3 to 40 V. |
| 16 | GND | power_in | Power ground return that connects to the common return point for all external MOSFET source connections. |
| 17 | IN5 | input | Gate drive 5 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V. |
| 18 | IN4 | input | Gate drive 4 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V. |
| 19 | IN3 | input | Gate drive 3 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V. |
| 20 | IN2 | input | Gate drive 2 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V. |
| 21 | IN1 | input | Gate drive 1 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V. |
| 22 | IN0 | input | Gate drive 0 active-high control input with internal pull-down to GND, rated -0.3 to 6.5 V. |
| 23 | CSN | input | Active-low serial interface chip select with pull-up resistor; data is latched into the serial register when CSN goes high, rated -0.3 to 6.5 V. |
| 24 | SI | input | Active-high serial data input with pull-down resistor, clocked into the serial register on the rising edge of SCK, rated -0.3 to 6.5 V. |
| 25 | SCK | input | Serial interface clock input with pull-down resistor, rated -0.3 to 6.5 V. |
| 26 | SO | output | Push-pull serial data output that carries fault register data on the falling edge of SCK and goes high impedance when CSN is high, rated -0.3 to 6.5 V. |
| 27 | RESETN | input | Active-low chip reset input that forces outputs low, resets the configuration and clears channel faults when held low longer than the minimum reset pulse width, rated -0.3 to 6.5 V. |
| 28 | VDD | power_in | Positive logic supply for digital inputs, outputs and logic, with an absolute maximum rating of -0.3 to 6.5 V. |
| 29 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-28-EP |
| Category | Power Management ICs |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Supply Voltage | VBB | -0.3 |  | 40 | V | with respect to ground at TA = 25°C | 2 |
| Logic Supply Voltage | VDD | -0.3 |  | 6.5 | V | with respect to ground at TA = 25°C | 2 |
| Gate Drive Supply Voltage | VDR | -0.3 |  | 6.5 | V | with respect to ground at TA = 25°C | 2 |
| Terminal VREG | VREG | -0.3 |  | 20 | V | with respect to ground at TA = 25°C | 2 |
| Terminals GATx | GATx | -0.3 |  | 6.5 | V | with respect to ground at TA = 25°C | 2 |
| Terminals DRNx | DRNx | -0.3 |  | 50 | V | with respect to ground at TA = 25°C | 2 |
| Terminals INx | INx | -0.3 |  | 6.5 | V | with respect to ground at TA = 25°C | 2 |
| Terminals SI, SCK, CSN |  | -0.3 |  | 6.5 | V | with respect to ground at TA = 25°C | 2 |
| Terminal SO | SO | -0.3 |  | 6.5 | V | with respect to ground at TA = 25°C | 2 |
| Terminal RESETN | RESETN | -0.3 |  | 6.5 | V | with respect to ground at TA = 25°C | 2 |
| Drain Feedback Clamp Energy | EDRNC |  |  | 10 | µJ | Single pulse less than 2 ms | 2 |
| Drain Feedback Clamp Current | IDRNC |  |  | 100 | mA | Single pulse not exceeding EDRN or PDRN | 2 |
| Drain Feedback Clamp Power | PDRNC |  |  | 100 | mW | Average power over any 2 ms period | 2 |
| Junction Temperature | TJ(max) |  |  | 150 | °C |  | 2 |
| Transient Junction Temperature | TtJ |  |  | 175 | °C | Overtemperature event not exceeding 10 s, lifetime duration not exceeding 10 hours | 2 |
| Storage Temperature Range | Tstg | -55 |  | 150 | °C |  | 2 |
| Operating Temperature Range, Range K | TA | -40 |  | 150 | °C | Range K | 2 |
| Logic Supply Voltage | VDD | 3 |  | 5.5 | V | Valid at TJ = -40°C to 150°C | 6 |
| Analog Supply Voltage | VBB | 6 |  | 40 | V | Valid at TJ = -40°C to 150°C | 6 |
| Gate Drive Supply Voltage | VDR | 3 |  | 6 | V | Valid at TJ = -40°C to 150°C | 6 |
| VDD Quiescent Current | IDDQ |  |  | 3 | mA |  | 6 |
| VBB Quiescent Current | IBBQ |  |  | 4 | mA |  | 6 |
| VBB Quiescent Current | IBBQ |  |  | 10 | µA | VDD = 0, VBB ≤ 30 V | 6 |
| VDR Quiescent Current | IDRQ |  |  | 4 | mA |  | 6 |
| Regulator Voltage | VREG | 17.5 |  | 18.5 | V | VBB > 19.5 V | 6 |
| Regulator Dropout | VDO | 0 |  | 0.6 | V |  | 6 |
| RESETN Pulse Width | tRST | 1 |  |  | µs |  | 6 |
| RESETN Glitch Filter | tRGF |  |  | 200 | ns |  | 6 |
| Oscillator Frequency | fOSC | 1.4 | 2 | 2.6 | MHz |  | 6 |
| Input High Voltage | VIH | 70 |  |  | %VDD |  | 6 |
| Input Low Voltage | VIL |  |  | 30 | %VDD |  | 6 |
| Input Hysteresis | VIhys | 300 | 500 |  | mV |  | 6 |
| SO Output Low Voltage | VOL |  | 0.2 | 0.4 | V | SO, IOL = 2 mA | 6 |
| SO Output Leakage | IL | -1 |  | 1 | µA | CSN = VDD | 6 |
| Pull-Up On-Resistance | RDS(on)UP |  | 50 | 70 | Ω | TJ = 25°C, IGHx = -20 mA | 6 |
| Pull-Up On-Resistance | RDS(on)UP |  | 75 | 125 | Ω | TJ = 150°C, IGHx = -20 mA | 6 |
| Pull-Down On-Resistance | RDS(on)DN |  | 50 | 95 | Ω | TJ = 25°C, IGLx = 20 mA | 6 |
| Pull-Down On-Resistance | RDS(on)DN |  | 75 | 145 | Ω | TJ = 150°C, IGLx = 20 mA | 6 |
| Output Sink Current | IGL | 20 |  |  | mA | GATx off, VGATx = VDR | 6 |
| Output Source Current | IGH |  |  | -40 | mA | GATx on, VGATx = 0 V | 6 |
| Minimum On-Time | ton |  |  | 1 | µs | At INx input | 6 |
| Minimum Off-Time | toff |  |  | 1 | µs | At INx input | 6 |
| RESETN to GATx |  |  | 0.5 | 1 | µs |  | 6 |
| Drain Clamp Voltage | VDCL | 45 |  |  | V | IDRNx = 10 µA | 7 |
| Drain Clamp Leakage | IDC |  |  | 1 | µA | VDRNx < 32 V | 7 |
| VDD Undervoltage Lockout | VDDUV | 2.6 | 2.75 | 2.9 | V | Decreasing VDD | 8 |
| VREG Undervoltage Lockout | VREGUV | 4.5 | 4.8 | 5.1 | V | Decreasing VREG | 8 |
| Overtemperature Warning Threshold | TJW | 145 | 160 | 175 | ºC | Temperature increasing | 8 |
| Short-to-Battery Threshold | VSTB | 30 | 31 | 32 | %VREG | GATx driven high, SB[2:0] = 111 | 7 |
| Pull-Up Diagnostic Current | IDPU | -80 | -65 | -50 | µA | GATx low, VDRNx < (VOCL, 200 mV) | 7 |
| Pull-Down Diagnostic Current | IDPD | 50 | 65 | 80 | µA | GATx low, NPD = 0, VDRNx >(VOCL + 200 mV) | 7 |
| Short-to-Ground Threshold | VSTG | 65 | 66 | 67 | %VREG | GATx driven low, SG = 1 | 7 |
| Short-to-Ground Threshold | VSTG | 44 | 45 | 46 | %VREG | GATx driven low, SG = 0 | 7 |
| Open-Load Threshold | VOL | 75 | 76 | 77 | %VREG | GATx driven low | 7 |
| Open-Load Clamp Voltage | VOCL | 70 | 71 | 72 | %VREG |  | 7 |
| Package Thermal Resistance, Junction to Ambient | RθJA |  | 28 |  | ºC/W | 4-layer PCB based on JEDEC standard | 2 |
| Package Thermal Resistance, Junction to Ambient | RθJA |  | 32 |  | ºC/W | 2-layer PCB with 3.8 in.2 of copper area each side | 2 |
| Package Thermal Resistance, Junction to Pad | RθJP |  | 2 |  | ºC/W |  | 2 |
| Drain Clamp Voltage | VDCL |  | 54 |  | V | IDRNx = 10 mA | 7 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | LP) with an exposed thermal pad. The package is lead (Pb) free with 100% matte-tin leadframe plating. | 1 |

## CAD (KiCad official)

- Symbol: `A3944KLPTR-T`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: TSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files: `a3944klptr-t-etched.step` / `a3944klptr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a3944klptr-t.step` / `a3944klptr-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a3944klptr-t-datasheet.pdf) (31 pp, sha256 `01679bb65c0b7218`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a3944klptr-t-datasheet.pdf)