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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

A3930KJPTR-T

Allegro MicroSystems LLC · Brushless DC (BLDC) Motor Driver · LQFP-48-EP(7x7)

A3930KJPTR-T from Allegro MicroSystems LLC, in a LQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	N.C.	unconnected	No connection.
2	RESET	input	Sleep mode control input; when low disables all circuits and draws ≤10 µA; input high threshold 2.2 V with 50 kΩ internal pull-down.
3	V5BD	output	5V base drive output for external regulator transistor QV5; provides up to 2 mA drive current.
4	V5	power_out	5V reference output (4.75 to 5.25 V); powers Hall pull-ups and logic; requires ≥200 nF decoupling to AGND.
5	FF2	output	Open drain fault flag output (active low); asserts for short-to-ground, short-to-supply, shorted winding, and low load faults.
6	FF1	output	Open drain fault flag output (active low); asserts for undervoltage, overtemperature, logic faults, and low load faults.
7	TACHO	output	Tachometer output toggling at each motor commutation; VOH = V5 - 1 V typical, VOL ≤0.4 V.
8	BRAKE	input	Active low brake input; shorts motor windings through low-side FETs when low; overridden by RESET or COAST.
9	DIR	input	Direction control input (VIL ≤0.8 V, VIH ≥2 V); high for forward, low for reverse per Hall commutation sequence.
10	H1	input	Hall sensor input with 100 kΩ pull-up to V5 and 500 mV hysteresis; 120° electrical spacing with internal filtering.
11	H2	input	Hall sensor input with 100 kΩ pull-up to V5 and 500 mV hysteresis; 120° electrical spacing with internal filtering.
12	H3	input	Hall sensor input with 100 kΩ pull-up to V5 and 500 mV hysteresis; 120° electrical spacing with internal filtering.
13	N.C.	unconnected	No connection.
14	PWM	input	External PWM control input; high enables drivers per Hall inputs, low disables for current recirculation.
15	MODE	input	Decay mode input; high for slow decay (high-side off only), low for fast decay (both high and low-side off).
16	RC	input	Oscillator timing input; fOSC ≈1/(RT×CT + tBLANK + tDEAD) with RT=5 to 400 kΩ; pull to AGND to disable PWM.
17	TEST	input	Production test pin for Allegro use only; must be connected to AGND during normal operation.
18	RDEAD	input	Dead time resistor connection; RDEAD (10 to 100 kΩ optimal) sets cross-conduction protection delay tDEAD.
19	CSOUT	output	Current sense amplifier output; VCSOUT ≈VOOS + 19×(CSP - CSN), output range 0.1 to V5 - 0.2 V, output impedance ~80 Ω.
20	REF	input	Current limit reference input; clamped internally to 4 V; typical pull-up RREF = 20 to 200 kΩ to V5.
21	CSN	input	Differential amplifier inverting input; connect to negative terminal of current sense resistor; input impedance ~4 kΩ.
22	CSP	input	Differential amplifier non-inverting input; connect to positive terminal of current sense resistor; input impedance ~80 kΩ.
23	VDSTH	input	Fault threshold voltage input (0.3 to 4 V range); sets drain-source voltage threshold for short-circuit detection.
24	VDRAIN	input	High-impedance drain voltage sense input (7 to 45 V operating range); Kelvin connection to high-side FET drains.
25	SC	passive	Phase C motor connection and bootstrap supply node; driven by external FETs; charges bootstrap capacitor CC when low.
26	GHC	output	High-side gate driver output for phase C; driven from bootstrap capacitor CC; output on-resistance ~4 Ω typical.
27	CC	passive	Bootstrap capacitor connection for phase C; charged to VREG (~13 V) when SC is low; supplies high-side gate drive.
28	SB	passive	Phase B motor connection and bootstrap supply node; driven by external FETs; charges bootstrap capacitor CB when low.
29	GHB	output	High-side gate driver output for phase B; driven from bootstrap capacitor CB; output on-resistance ~4 Ω typical.
30	CB	passive	Bootstrap capacitor connection for phase B; charged to VREG (~13 V) when SB is low; supplies high-side gate drive.
31	SA	passive	Phase A motor connection and bootstrap supply node; driven by external FETs; charges bootstrap capacitor CA when low.
32	GHA	output	High-side gate driver output for phase A; driven from bootstrap capacitor CA; output on-resistance ~4 Ω typical.
33	CA	passive	Bootstrap capacitor connection for phase A; charged to VREG (~13 V) when SA is low; supplies high-side gate drive.
34	GLC	output	Low-side gate driver output for phase C; logic level output VOH = VREG - 0.2 V typical, VOL ≤0.4 V; pull-down impedance ~1.5 Ω.
35	GLB	output	Low-side gate driver output for phase B; logic level output VOH = VREG - 0.2 V typical, VOL ≤0.4 V; pull-down impedance ~1.5 Ω.
36	GLA	output	Low-side gate driver output for phase A; logic level output VOH = VREG - 0.2 V typical, VOL ≤0.4 V; pull-down impedance ~1.5 Ω.
37	N.C.	unconnected	No connection.
38	LSS	passive	Low-side source return connection; common source point for all low-side external FETs; gate discharge return path.
39	ESF	input	Enable Stop on Fault (active high) logic input; when high, short-circuit faults disable all outputs and latch; when low, faults only flag via FF pins.
40	VREG	power_out	Gate driver supply output from internal charge pump (~13 V nominal); supplies all gate drivers and bootstrap charging; requires ≥20 µF storage capacitor.
41	AGND	power_in	Analog ground reference for all logic, control, and power circuits; exposed thermal pad also connected; critical for timing and current sense accuracy.
42	CP1	passive	Charge pump capacitor positive terminal; connect 470 nF ceramic capacitor between CP1 and CP2 to generate VREG.
43	CP2	passive	Charge pump capacitor negative terminal; connect 470 nF ceramic capacitor between CP1 and CP2 to generate VREG.
44	DIRO	output	Direction output indicating measured motor rotation direction; high for forward, low for reverse per commutation table; VOH = V5 - 1 V typical.
45	VBB	power_in	Main power supply input; operating range 5.5 to 50 V (guaranteed function 7 to 45 V); quiescent current 11 to 14 mA; requires 100 nF + 10 µF parallel decoupling.
46	COAST	input	Active low coast input; when low, disables all gate drive outputs (coasts motor) without disabling supplies or logic; functions as emergency stop.
47	N.C.	unconnected	No connection.
48	N.C.	unconnected	No connection.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems LLC
Package	LQFP-48-EP(7x7)
Category	Motor Driver ICs
Pins	49

CAD (KiCad official)

Symbol: A3930KJPTR-T
Footprint: Package_QFP:LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm
3D model: LQFP-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: a3930kjptr-t-etched.step / a3930kjptr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a3930kjptr-t.step / a3930kjptr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems LLC datasheet (21 pp, sha256 468cfb1c44c4baf5, retrieved 2026-09-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF