A3921KLPTR-T

{
  "slug": "a3921klptr-t",
  "version": "0.1.0",
  "type": "component",
  "description": "Allegro MicroSystems LLC Brushed DC Motor Drivers, TSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "motor driver ics",
    "a3921klptr-t",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "a3921klptr-t.kicad_sym",
    "a3921klptr-t.kicad_mod",
    "a3921klptr-t.glb",
    "a3921klptr-t.step",
    "a3921klptr-t.lbr",
    "docs/hero.png",
    "docs/a3921klptr-t-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "a3921klptr-t-hero.glb",
    "a3921klptr-t-hero.overlay.json",
    "a3921klptr-t-etched.glb"
  ],
  "component": {
    "mpn": "A3921KLPTR-T",
    "manufacturer": "Allegro MicroSystems LLC",
    "package": "TSSOP-28-EP",
    "pin_count": 29,
    "category": "Motor Driver ICs",
    "subcategory": "Brushed DC Motor Drivers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908650219900928",
    "parts": {
      "symbol": "a3921klptr-t.kicad_sym",
      "footprint": "a3921klptr-t.kicad_mod",
      "model_3d": "a3921klptr-t-hero.glb",
      "model_3d_plain": "a3921klptr-t-etched.glb",
      "model_3d_step": "a3921klptr-t-etched.step",
      "model_3d_step_plain": "a3921klptr-t.step",
      "lbr": "a3921klptr-t.lbr"
    },
    "distributor_links": {
      "lcsc": "C459251",
      "digikey": "620-1523-2-ND",
      "mouser": "250-A3921KLPTR-T"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T03:49:33Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "620-1523-2-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "250-A3921KLPTR-T",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDRAIN",
        "type": "input",
        "description": "High-side common drain sense input, to be connected directly to the common drain point of the power bridge FETs; its input current is about 72 × VDSTH + 52 µA (µA, with VDSTH in V)."
      },
      {
        "number": "2",
        "name": "LSS",
        "type": "power_in",
        "description": "Low-side common source return path for gate discharge, to be tied to the low-side FET sources through an independent low-impedance connection and not directly to GND."
      },
      {
        "number": "3",
        "name": "GLB",
        "type": "output",
        "description": "Low-side gate drive output B for the external N-channel low-side FET; sources current to turn on and sinks to LSS to turn off."
      },
      {
        "number": "4",
        "name": "SB",
        "type": "passive",
        "description": "Load connection B, sensing the voltage switched across the load and serving as the negative supply connection for the phase B high-side drive."
      },
      {
        "number": "5",
        "name": "GHB",
        "type": "output",
        "description": "High-side gate drive output B for the external N-channel high-side FET; sources current to turn on and sinks to SB to turn off."
      },
      {
        "number": "6",
        "name": "CB",
        "type": "passive",
        "description": "Bootstrap capacitor B high-side connection and positive supply for the phase B high-side gate drive."
      },
      {
        "number": "7",
        "name": "NC",
        "type": "unconnected",
        "description": "No connection."
      },
      {
        "number": "8",
        "name": "VREG",
        "type": "power_out",
        "description": "Regulated supply, nominally 13 V, that powers the low-side gate drivers and bootstrap charging and needs a storage capacitor (about 20 × CBOOT) close to the pin."
      },
      {
        "number": "9",
        "name": "CA",
        "type": "passive",
        "description": "Bootstrap capacitor A high-side connection and positive supply for the phase A high-side gate drive."
      },
      {
        "number": "10",
        "name": "GHA",
        "type": "output",
        "description": "High-side gate drive output A for the external N-channel high-side FET; sources current to turn on and sinks to SA to turn off."
      },
      {
        "number": "11",
        "name": "SA",
        "type": "passive",
        "description": "Load connection A, sensing the voltage switched across the load and serving as the negative supply connection for the phase A high-side drive."
      },
      {
        "number": "12",
        "name": "GLA",
        "type": "output",
        "description": "Low-side gate drive output A for the external N-channel low-side FET; sources current to turn on and sinks to LSS to turn off."
      },
      {
        "number": "13",
        "name": "VBB",
        "type": "power_in",
        "description": "Main load supply, specified for 7 to 50 V with functional operation down to 5.5 V, decoupled with a ceramic capacitor close to the VBB and GND pins."
      },
      {
        "number": "14",
        "name": "NC",
        "type": "unconnected",
        "description": "No connection."
      },
      {
        "number": "15",
        "name": "CP2",
        "type": "passive",
        "description": "Charge pump capacitor terminal 2; a pump capacitor of at least 220 nF (typically 470 nF) is connected between CP1 and CP2."
      },
      {
        "number": "16",
        "name": "CP1",
        "type": "passive",
        "description": "Charge pump capacitor terminal 1; a pump capacitor of at least 220 nF (typically 470 nF) is connected between CP1 and CP2."
      },
      {
        "number": "17",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device; the sensitive RDEAD and VDSTH connections must be referenced directly to this pin."
      },
      {
        "number": "18",
        "name": "NC",
        "type": "unconnected",
        "description": "No connection."
      },
      {
        "number": "19",
        "name": "PHASE",
        "type": "input",
        "description": "Phase control input that sets the positive load current direction and doubles as a PWM input for fast-decay four-quadrant control."
      },
      {
        "number": "20",
        "name": "V5",
        "type": "power_out",
        "description": "Integrated 5 V logic supply regulator output (4.5 to 5.5 V at no load), used for external pullups and requiring at least 100 nF decoupling to GND."
      },
      {
        "number": "21",
        "name": "SR",
        "type": "input",
        "description": "Synchronous rectification enable input; high enables synchronous rectification during PWM off time, low disables it."
      },
      {
        "number": "22",
        "name": "PWML",
        "type": "input",
        "description": "Low-side PWM control input that chops the low-side FETs; PWML and PWMH can be tied together for fast-decay PWM."
      },
      {
        "number": "23",
        "name": "PWMH",
        "type": "input",
        "description": "High-side PWM control input that chops the high-side FETs; PWMH and PWML can be tied together for fast-decay PWM."
      },
      {
        "number": "24",
        "name": "RESET",
        "type": "input",
        "description": "Active-low reset input that puts the device into sleep mode when held low and clears latched faults on a pulse shorter than tRES (0.1 to 3.5 µs); it has a 50 kΩ internal pulldown."
      },
      {
        "number": "25",
        "name": "FF1",
        "type": "output",
        "description": "Open-drain Fault Flag 1 output, used with FF2 to signal fault conditions per Table 3 (VFF(L) at most 0.4 V at 1 mA when no fault is present)."
      },
      {
        "number": "26",
        "name": "FF2",
        "type": "output",
        "description": "Open-drain Fault Flag 2 output, used with FF1 to signal fault conditions per Table 3 (VFF(L) at most 0.4 V at 1 mA when no fault is present)."
      },
      {
        "number": "27",
        "name": "RDEAD",
        "type": "passive",
        "description": "Dead-time setting input; a resistor between RDEAD and GND from 3 kΩ to 240 kΩ sets tDEAD, and connecting it directly to V5 selects the default 6 µs typical dead time."
      },
      {
        "number": "28",
        "name": "VDSTH",
        "type": "input",
        "description": "VDS fault threshold input, with a valid range of 0.1 to 2 V; connecting it to V5 or above the 4.95 V disable threshold disables the FET short-circuit detection."
      },
      {
        "number": "29",
        "name": "PAD",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin types for LSS, SB, SA, CA, CB, CP1, CP2, VDRAIN and RDEAD are not stated as ERC classes in the d; Exposed pad is listed in Table 4 as 'PAD' rather than a numbered pin; it is included as a separate e; The datasheet specifies the LP (TSSOP-28 with exposed pad) package for the A3921KLPTR-T, so this pin",
          "exposed pad 29 added from the footprint",
          "dropped thermal pad ['EP'] absent from footprint"
        ],
        "pages_sent": 21,
        "cost_usd": 0.138,
        "at": "2026-10-19T03:48:00"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908650219900928",
        "pages": 21,
        "sha256": "32208e8ce1b5a970",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 29,
        "described": 29,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "a3921klptr-t.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.2,
          9.7,
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        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "ff242f1d3be9d09e7f929707a2c5b1ee974a4f882053b04bcdb1cd2cb21223ef",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "a3921klptr-t-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
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        "footprint_binding": "identity",
        "sha256": "479f8de3490a86556c8452c4fc0b277d699465b37b8d70e9d5bd74f8f5b4ea9d",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}