# A3921KLPTR-T

**Allegro MicroSystems LLC** · Brushed DC Motor Drivers · TSSOP-28-EP

A3921KLPTR-T from Allegro MicroSystems LLC, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDRAIN | input | High-side common drain sense input, to be connected directly to the common drain point of the power bridge FETs; its input current is about 72 × VDSTH + 52 µA (µA, with VDSTH in V). |
| 2 | LSS | power_in | Low-side common source return path for gate discharge, to be tied to the low-side FET sources through an independent low-impedance connection and not directly to GND. |
| 3 | GLB | output | Low-side gate drive output B for the external N-channel low-side FET; sources current to turn on and sinks to LSS to turn off. |
| 4 | SB | passive | Load connection B, sensing the voltage switched across the load and serving as the negative supply connection for the phase B high-side drive. |
| 5 | GHB | output | High-side gate drive output B for the external N-channel high-side FET; sources current to turn on and sinks to SB to turn off. |
| 6 | CB | passive | Bootstrap capacitor B high-side connection and positive supply for the phase B high-side gate drive. |
| 7 | NC | unconnected | No connection. |
| 8 | VREG | power_out | Regulated supply, nominally 13 V, that powers the low-side gate drivers and bootstrap charging and needs a storage capacitor (about 20 × CBOOT) close to the pin. |
| 9 | CA | passive | Bootstrap capacitor A high-side connection and positive supply for the phase A high-side gate drive. |
| 10 | GHA | output | High-side gate drive output A for the external N-channel high-side FET; sources current to turn on and sinks to SA to turn off. |
| 11 | SA | passive | Load connection A, sensing the voltage switched across the load and serving as the negative supply connection for the phase A high-side drive. |
| 12 | GLA | output | Low-side gate drive output A for the external N-channel low-side FET; sources current to turn on and sinks to LSS to turn off. |
| 13 | VBB | power_in | Main load supply, specified for 7 to 50 V with functional operation down to 5.5 V, decoupled with a ceramic capacitor close to the VBB and GND pins. |
| 14 | NC | unconnected | No connection. |
| 15 | CP2 | passive | Charge pump capacitor terminal 2; a pump capacitor of at least 220 nF (typically 470 nF) is connected between CP1 and CP2. |
| 16 | CP1 | passive | Charge pump capacitor terminal 1; a pump capacitor of at least 220 nF (typically 470 nF) is connected between CP1 and CP2. |
| 17 | GND | power_in | Ground reference for the device; the sensitive RDEAD and VDSTH connections must be referenced directly to this pin. |
| 18 | NC | unconnected | No connection. |
| 19 | PHASE | input | Phase control input that sets the positive load current direction and doubles as a PWM input for fast-decay four-quadrant control. |
| 20 | V5 | power_out | Integrated 5 V logic supply regulator output (4.5 to 5.5 V at no load), used for external pullups and requiring at least 100 nF decoupling to GND. |
| 21 | SR | input | Synchronous rectification enable input; high enables synchronous rectification during PWM off time, low disables it. |
| 22 | PWML | input | Low-side PWM control input that chops the low-side FETs; PWML and PWMH can be tied together for fast-decay PWM. |
| 23 | PWMH | input | High-side PWM control input that chops the high-side FETs; PWMH and PWML can be tied together for fast-decay PWM. |
| 24 | RESET | input | Active-low reset input that puts the device into sleep mode when held low and clears latched faults on a pulse shorter than tRES (0.1 to 3.5 µs); it has a 50 kΩ internal pulldown. |
| 25 | FF1 | output | Open-drain Fault Flag 1 output, used with FF2 to signal fault conditions per Table 3 (VFF(L) at most 0.4 V at 1 mA when no fault is present). |
| 26 | FF2 | output | Open-drain Fault Flag 2 output, used with FF1 to signal fault conditions per Table 3 (VFF(L) at most 0.4 V at 1 mA when no fault is present). |
| 27 | RDEAD | passive | Dead-time setting input; a resistor between RDEAD and GND from 3 kΩ to 240 kΩ sets tDEAD, and connecting it directly to V5 selects the default 6 µs typical dead time. |
| 28 | VDSTH | input | VDS fault threshold input, with a valid range of 0.1 to 2 V; connecting it to V5 or above the 4.95 V disable threshold disables the FET short-circuit detection. |
| 29 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | TSSOP-28-EP |
| Category | Motor Driver ICs |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage Functional Operating Range | VBB | 5.5 |  | 50 | V |  | 5 |
| Load Supply Quiescent Current | IBBQ |  | 10 | 14 | mA | RESET = high, outputs = low, VBB = 12 V | 5 |
| Load Supply Sleep Current | IBBS |  |  | 10 | µA | RESET = low, Sleep mode, VBB = 12 V | 5 |
| VREG Output Voltage | VREG | 12.5 | 13 | 13.75 | V | VBB > 9 V, IREG = 0 to 10 mA | 5 |
| VREG Output Voltage | VREG | 8.5 | 9.5 |  | V | 5.5 V < VBB ≤ 6 V, IREG < 5.5 mA | 5 |
| V5 Output Voltage | V5(out) | 4.5 | 5 | 5.5 | V | No load | 5 |
| V5 Line Regulation | V5(line) |  | 15 | 40 | mV | I5 = -2 mA | 5 |
| V5 Load Regulation | V5(load) |  | 50 | 100 | mV | I5 = 0 to -2 mA | 5 |
| V5 Short-Circuit Current | I5M |  | 28 | 35 | mA | VBB = 40 V, V5 = 0 V | 5 |
| Bootstrap Diode Forward Voltage | VfBOOT | 0.4 | 0.7 | 1 | V | ID = 10 mA | 5 |
| Bootstrap Diode Forward Voltage | VfBOOT | 1.5 | 2.2 | 2.8 | V | ID = 100 mA | 5 |
| Bootstrap Diode Resistance | rD | 6 | 10 | 20 | Ω | rD(100mA) = (VfBOOT(150mA), VfBOOT(50mA)) / 100 mA | 5 |
| Bootstrap Diode Current Limit | IDBOOT | 250 | 500 | 750 | mA |  | 5 |
| High-Side Gate Drive Static Load Resistance | RGSH | 250 |  |  | kΩ |  | 5 |
| Pullup On Resistance | RDS(on)UP | 6 | 8 | 12 | Ω | TJ = 25°C, IGHx = -150 mA | 5 |
| Pullup On Resistance | RDS(on)UP | 10 | 13 | 16 | Ω | TJ = 150°C, IGHx = -150 mA | 5 |
| Pulldown On Resistance | RDS(on)DN | 2 | 3 | 4 | Ω | TJ = 25°C, IGLx = 150 mA | 5 |
| Pulldown On Resistance | RDS(on)DN | 3 | 4.5 | 6 | Ω | TJ = 150°C, IGLx = 150 mA | 5 |
| Turn-Off Propagation Delay | tP(off) | 60 | 90 | 150 | ns | Input change to unloaded gate output change | 5 |
| Turn-On Propagation Delay | tP(on) | 60 | 90 | 150 | ns | Input change to unloaded gate output change | 5 |
| Dead Time | tDEAD | 815 | 960 | 1110 | ns | RDEAD = 30 kΩ | 6 |
| FF1 and FF2 Fault Output Low Voltage | VFF(L) |  |  | 0.4 | V | IFF = 1 mA, fault not present | 6 |
| FF1 and FF2 Fault Output Leakage Current | IFF(H) | -1 |  | 1 | µA | VFF = 5 V, fault present | 6 |
| RDEAD Current | IDEAD | -200 |  | -70 | µA | RDEAD = GND | 6 |
| Input Low Voltage | VIN(L) |  |  | 0.8 | V |  | 6 |
| Input High Voltage | VIN(H) | 2 |  |  | V |  | 6 |
| Input Hysteresis (Except RESET Pin) | VINhys | 100 | 250 |  | mV |  | 6 |
| Input Hysteresis (RESET Pin) | VINRSThys | 200 |  |  | mV |  | 6 |
| Input Current (Except RESET Pin) | IIN | -1 |  | 1 | µA | 0 V < VIN < V5 | 6 |
| RESET Pulse Time | tRES | 0.1 |  | 3.5 | µs |  | 6 |
| VREG Undervoltage Lockout Threshold (rising) | VREGUVon | 7.5 | 8 | 8.5 | V | VREG rising | 6 |
| VREG Undervoltage Lockout Threshold (falling) | VREGUVoff | 6.75 | 7.25 | 7.75 | V | VREG falling | 6 |
| Bootstrap Undervoltage Threshold | VBOOTUV | 59 |  | 69 | %VREG | Cx with respect to Sx | 6 |
| V5 Undervoltage Turn-Off Threshold | V5UVoff | 3.4 | 3.6 | 3.8 | V | V5 falling | 6 |
| V5 Undervoltage Hysteresis | V5UVhys | 300 | 400 | 500 | mV |  | 6 |
| VDSTH Input Range | VDSTH | 0.1 |  | 2 | V |  | 6 |
| VDSTH Input Current | IDSTH |  | 10 | 30 | µA | 0 V < VDSTH < 2 V | 6 |
| VDSTH Disable Voltage | VDSDIS | 4.95 |  |  | V | When not connected directly to V5 | 6 |
| VDRAIN Input Current | IDRAIN |  |  | 250 | µA | VDSTH = 2 V, VBB = 12 V, 0 V < VDRAIN < VBB | 6 |
| Short-to-Ground Threshold Offset (high-side on, VDSTH ≥ 1 V) | VSTGO | -100 |  | 100 | mV | High-side on, VDSTH ≥ 1 V | 6 |
| Short-to-Ground Threshold Offset (high-side on, VDSTH < 1 V) | VSTGO | -150 |  | 150 | mV | High-side on, VDSTH < 1 V | 6 |
| Short-to-Battery Threshold Offset (low-side on, VDSTH ≥ 1 V) | VSTBO | -100 |  | 100 | mV | Low-side on, VDSTH ≥ 1 V | 6 |
| Short-to-Battery Threshold Offset (low-side on, VDSTH < 1 V) | VSTBO | -150 |  | 150 | mV | Low-side on, VDSTH < 1 V | 6 |
| Overtemperature Fault Flag Threshold | TJF | 150 | 170 |  | ºC | Temperature increasing | 6 |
| Load Supply Voltage | VBB | -0.3 |  | 50 | V | With respect to GND | 2 |
| V5 Pin | V5 | -0.3 |  | 7 | V | With respect to GND | 2 |
| LSS Pin | LSS | -4 |  | 6.5 | V | With respect to GND | 2 |
| VDSTH Pin | VDSTH | -0.3 |  | 6.5 | V | With respect to GND | 2 |
| SA and SB Pins |  | -5 |  | 55 | V | With respect to GND | 2 |
| VDRAIN Pin | VDRAIN | -5 |  | 55 | V | With respect to GND | 2 |
| GLA and GLB Pins |  | -5 |  | 16 | V | With respect to GND | 2 |
| Operating Temperature Range | TA | -40 |  | 150 | ºC | Range K | 2 |
| Junction Temperature | TJ(max) |  |  | 150 | ºC |  | 2 |
| Transient Junction Temperature | TtJ |  |  | 175 | ºC | Overtemperature event not exceeding 1 s, lifetime duration not exceeding 10 hr | 2 |
| Storage Temperature Range | Tstg | -55 |  | 150 | ºC |  | 2 |
| Package Thermal Resistance, junction to ambient (4-layer PCB) | RθJA |  | 28 |  | ºC/W | 4-layer PCB based on JEDEC standard | 2 |
| Package Thermal Resistance, junction to ambient (2-layer PCB) | RθJA |  | 32 |  | ºC/W | 2-layer PCB with 3.8 in.² of copper area each side | 2 |
| Package Thermal Resistance, junction to pad | RθJP |  | 2 |  | ºC/W |  | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | an exposed thermal pad (suffix LP). This package is lead (Pb) free, with 100% matte-tin leadframe plating. | 1 |

## CAD (KiCad official)

- Symbol: `A3921KLPTR-T`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: TSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files: `a3921klptr-t-etched.step` / `a3921klptr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a3921klptr-t.step` / `a3921klptr-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems LLC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908650219900928) (21 pp, sha256 `32208e8ce1b5a970`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a3921klptr-t-datasheet.pdf)