component
A3918SESTR-T
Public Made by Adomby adom
Allegro MicroSystems LLC Brushed DC Motor Drivers, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownA3918SESTR-T
Allegro MicroSystems LLC · Brushed DC Motor Drivers · QFN-16-EP(3x3)
A3918SESTR-T from Allegro MicroSystems LLC, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP2 | passive | Charge pump capacitor terminal 2; a 0.1 µF ceramic capacitor connects between CP1 and CP2 for pumping. |
| 2 | GND | power_in | Ground terminal that should connect to a low-impedance single-point star ground located very close to the device. |
| 3 | SLEEP | input | Active-low sleep logic input; VIN below 0.4 V puts the device in sleep mode (150 nA typ, 500 nA max) and a logic high allows normal operation. |
| 4 | IN1 | input | Control input 1 for PWM and direction control, with VIN(1) min 2.0 V, VIN(0) max 0.8 V, and absolute logic input range -0.3 to 7 V. |
| 5 | IN2 | input | Control input 2 for PWM and direction control, with VIN(1) min 2.0 V, VIN(0) max 0.8 V, and absolute logic input range -0.3 to 7 V. |
| 6 | GND | power_in | Ground terminal that should connect to a low-impedance single-point star ground located very close to the device. |
| 7 | FL | output | Current limit flag output that is pulled low when the peak current is reached, with asserted voltage max 200 mV at 1 mA and leakage max 1 µA; it does not affect driver operation. |
| 8 | GND | power_in | Ground terminal that should connect to a low-impedance single-point star ground located very close to the device. |
| 9 | VBB | power_in | Load supply voltage with operating range 2.5 to 9 V and absolute maximum 9.6 V. |
| 10 | OUTB | output | DMOS full-bridge output B driving the motor winding, with continuous output current rated at 1 A and peak 1.5 A (DC < 30%). |
| 11 | SENSE | passive | Current sense resistor terminal whose voltage must not exceed 0.5 V continuous or 1 V pulsed (tw < 1 µs), and which should be shorted to ground if internal current limiting is not used. |
| 12 | OUTA | output | DMOS full-bridge output A driving the motor winding, with continuous output current rated at 1 A and peak 1.5 A (DC < 30%). |
| 13 | VCP | passive | Reservoir capacitor terminal; a 0.1 µF ceramic capacitor is required between VCP and VBB to supply the high-side DMOS gates. |
| 14 | CP3 | passive | Charge pump capacitor terminal 3; a 0.1 µF ceramic capacitor connects between CP3 and CP4 for pumping. |
| 15 | CP1 | passive | Charge pump capacitor terminal 1; a 0.1 µF ceramic capacitor connects between CP1 and CP2 for pumping. |
| 16 | CP4 | passive | Charge pump capacitor terminal 4; a 0.1 µF ceramic capacitor connects between CP3 and CP4 for pumping. |
| 17 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | QFN-16-EP(3x3) |
| Category | Motor Driver ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Load Supply Voltage | VBB | 9.6 | V | 2 | |||
| Logic Input Voltage Range | VIN | -0.3 | 7 | V | 2 | ||
| Sense Voltage, continuous | VSENSE | 0.5 | V | Continuous | 2 | ||
| Sense Voltage, pulsed | VSENSE | 1 | V | Pulsed, tw < 1 µs | 2 | ||
| Output Current, continuous | IOUT | 1 | A | Continuous; may be limited by duty cycle, ambient temperature, and heat sinking | 2 | ||
| Output Current, peak | IOUT | 1.5 | A | Peak, DC < 30% | 2 | ||
| Operating Temperature Range | TA | -20 | 85 | °C | Range S | 2 | |
| Junction Temperature | TJ(max) | 150 | °C | 2 | |||
| Storage Temperature Range | Tstg | -40 | 150 | °C | 2 | ||
| Package Thermal Resistance | RθJA | 42 | ºC/W | 4-layer PCB based on JEDEC standard | 2 | ||
| Operating Voltage Range | VBB | 2.5 | 9 | V | 3 | ||
| VBB Supply Current (sleep mode) | IBB | 150 | 500 | nA | Sleep mode, VIN < 0.4 V | 3 | |
| Output Resistance, source driver | RDS(on) | 0.52 | 0.6 | Ω | Source driver, IOUT = 400 mA, VBB = 3 V, TJ = 25°C | 3 | |
| Output Resistance, sink driver | RDS(on) | 0.62 | 0.74 | Ω | Sink driver, IOUT = 400 mA, VBB = 3 V, TJ = 25°C | 3 | |
| Current Trip Sense Voltage | VSENSE | 160 | 200 | 240 | mV | FL falling edge | 3 |
| Clamp Diode Voltage | Vf | 1 | V | I = 400 mA | 3 | ||
| Output Leakage Current | IDSS | -20 | 20 | µA | Outputs, VOUT = 9 V | 3 | |
| Logic Input Voltage, high | VIN(1) | 2 | 5.5 | V | 3 | ||
| Logic Input Voltage, low | VIN(0) | 0.8 | V | 3 | |||
| Logic Input Current, high | IIN(1) | 500 | nA | VIN = 5.5 V | 3 | ||
| Logic Input Current, low | IIN(0) | -500 | nA | VIN = 0.8 V | 3 | ||
| SLEEP Input Voltage, low | VSLEEP(0) | 0.4 | V | 3 | |||
| SLEEP Input Voltage, high | VSLEEP(1) | 2 | V | 3 | |||
| Fault Output Voltage | VFL | 200 | mV | Flag asserted, IFL = 1 mA | 3 | ||
| Fault Output Leakage Current | IFL | 1 | µA | VFL = 5 V | 3 | ||
| Blank Time | tBLANK | 2.1 | 3 | 3.9 | µs | 3 | |
| Propagation Delay Time, on | tpd(on) | 100 | 235 | 350 | ns | Input high to source on, input low to source off | 3 |
| Propagation Delay Time, off | tpd(off) | 50 | 100 | 200 | ns | Input low to sink off, input high to sink on | 3 |
| Crossover Delay | tCOD | 200 | 425 | 650 | ns | 3 | |
| VBB Undervoltage Lockout Threshold | VBBUVLO | 2.2 | 2.31 | 2.45 | V | VBB rising | 3 |
| VBB Undervoltage Lockout Hysteresis | VBBUVHYS | 200 | 300 | 400 | mV | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. | 1 |
CAD (KiCad official)
- Symbol:
A3918SESTR-T - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
a3918sestr-t-etched.step/a3918sestr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a3918sestr-t.step/a3918sestr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (9 pp, sha256
3987b834a8bd9efc, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).