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A3916GESTR-T

Public Made by Adom

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Allegro MicroSystems, LLC Motor Driver ICs, WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A3916GESTR-T

Allegro MicroSystems, LLC · Motor Driver ICs · WQFN-16-EP(3x3)

A3916GESTR-T from Allegro MicroSystems, LLC, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground terminal.
2 SLEEPn input Active-low sleep input that minimizes power consumption (logic low below 0.4 V); wait 1.5 ms after wake before issuing commands.
3 IN1 input Control input for H-bridge 1 (logic high at least 2.0 V, low at most 0.8 V).
4 IN2 input Control input for H-bridge 1 (logic high at least 2.0 V, low at most 0.8 V).
5 IN3 input Control input for H-bridge 2 (logic high at least 2.0 V, low at most 0.8 V).
6 IN4 input Control input for H-bridge 2 (logic high at least 2.0 V, low at most 0.8 V).
7 FAULTn output Open-drain fault output pulled low during a TSD or overcurrent protection event (max 200 mV at 1 mA).
8 OUT2A output DMOS H-bridge 2 output A, rated for 1.0 A continuous.
9 SENSE2 passive Sense resistor terminal for bridge 2; ITRIP(max) = 0.2 V / RSENSE, max 0.5 V continuous, shorted to ground if current limiting is unused.
10 OUT2B output DMOS H-bridge 2 output B, rated for 1.0 A continuous.
11 VBB power_in Motor supply voltage, 2.7 to 15 V operating range.
12 OUT1B output DMOS H-bridge 1 output B, rated for 1.0 A continuous.
13 SENSE1 passive Sense resistor terminal for bridge 1; ITRIP(max) = 0.2 V / RSENSE, max 0.5 V continuous, shorted to ground if current limiting is unused.
14 OUT1A output DMOS H-bridge 1 output A, rated for 1.0 A continuous.
15 VCP passive Charge pump capacitor terminal; a 0.1 µF capacitor is shown in the typical application.
16 NC unconnected No internal connection.
17 PAD passive Exposed pad for enhanced thermal performance; thermal vias on a multilayer PCB can improve dissipation.

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package WQFN-16-EP(3x3)
Category Power Supply Chip
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VBB 15 V 2
Output Current IOUT 1 A Continuous 2
Output Current (parallel mode) IOUT(PAR) 1.8 A Continuous 2
Sense Voltage, continuous VSENSEx 0.5 V Continuous 2
Sense Voltage, pulsed VSENSEx 2.5 V Pulsed, tw < 1 µs 2
Logic Input Voltage Range VIO -0.3 5.5 V 2
Junction Temperature TJ(MAX) 150 °C 2
Storage Temperature Range Tstg -55 150 °C 2
Operating Temperature Range TA -40 105 °C Range G 2
Load Supply Voltage Range VBB 2.7 15 V Operating 5
Thermal Resistance Junction to Ambient RθJA 47 °C/W 3 × 3 mm ES package, 4-layer PCB based on JEDEC standard 2
High-side Output On Resistance RDS(ON,HS) 335 450 mΩ TJ = 25°C, 500 mA, VBB = 5 V 5
Low-side Output On Resistance RDS(ON,LS) 375 525 mΩ TJ = 25°C, 500 mA, VBB = 5 V 5
Diode Forward Voltage VF 0.85 1 V I = 500 mA 5
VBB Supply Current IBB(2p7V) 2.2 4.5 mA Outputs disabled, VBB = 2.7 V 5
VBB Supply Current IBB(15V) 3.1 4.5 mA Outputs disabled, VBB = 15 V 5
VBB Sleep Current IBB(SLEEP) 0.5 µA Sleep Mode 5
Logic Input Voltage High, INx VIN(1) 2 V 5
Logic Input Voltage Low, INx VIN(0) 0.8 V 5
Logic Input Voltage High, SLEEPn VIN(1) 2 V 5
Logic Input Voltage Low, SLEEPn VIN(0) 0.4 V 5
Logic Input Hysteresis VHYS 100 500 mV 5
Logic Input Current IIN 33 50 µA VIN = 3.3 V, pulldown = 100 kΩ 5
Fault Output Voltage VFAULTn 200 mV Flag asserted, IFAULTn = 1 mA 5
Fault Output Leakage Current IFAULTn 1 µA VFAULTn = 5 V 5
VSENSE Blank time tBLANK 2.1 3.1 4.1 µs 5
VSENSE Trip Voltage VTRIP 170 205 240 mV 5
Fixed Off-Time tOFF 20 30 40 µs 5
Crossover Delay tOCD 200 550 1000 ns 5
VBB Undervoltage Lockout VBB(UVLO) 2.55 2.65 V VBB rising 5
Thermal Shutdown Temperature TJ1 150 165 180 °C 5
High-side Output On Resistance RDS(ON,HS) 410 mΩ TJ = 85°C, 500 mA, VBB = 5 V 5
Low-side Output On Resistance RDS(ON,LS) 455 mΩ TJ = 85°C, 500 mA, VBB = 5 V 5
VBB Hysteresis VBB(UVLO,HYS) 125 mV 5
Thermal Shutdown Hysteresis ΔTJ1 20 °C 5

CAD (KiCad official)

  • Symbol: A3916GESTR-T
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: a3916gestr-t-etched.step / a3916gestr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a3916gestr-t.step / a3916gestr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (11 pp, sha256 c20cabcce3abe991, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF