component
A3916GESTR-T-1
Public Made by Adomby adom
Allegro MicroSystems LLC Stepper Motor Driver, QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownA3916GESTR-T-1
Allegro MicroSystems LLC · Stepper Motor Driver · QFN-20-EP(4x4)
A3916GESTR-T-1 from Allegro MicroSystems LLC, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection on the 20-contact ES,-1 package. |
| 2 | GND | power_in | Ground terminal for the device, serving as the ground reference for the A3916. |
| 3 | SLEEPn | input | Active-low sleep input where a logic high allows normal operation, with VIN(1) of at least 2.0 V and VIN(0) of at most 0.4 V, and the device needs 1.5 ms after leaving sleep before a command is issued. |
| 4 | IN1 | input | Bridge 1 control input with VIN(1) of at least 2.0 V, VIN(0) of at most 0.8 V, and a logic input voltage range of -0.3 to 5.5 V. |
| 5 | IN2 | input | Bridge 1 control input with VIN(1) of at least 2.0 V, VIN(0) of at most 0.8 V, and a logic input voltage range of -0.3 to 5.5 V. |
| 6 | IN3 | input | Bridge 2 control input with VIN(1) of at least 2.0 V, VIN(0) of at most 0.8 V, and a logic input voltage range of -0.3 to 5.5 V. |
| 7 | IN4 | input | Bridge 2 control input with VIN(1) of at least 2.0 V, VIN(0) of at most 0.8 V, and a logic input voltage range of -0.3 to 5.5 V. |
| 8 | FAULTn | output | Open-drain fault output pulled low during a thermal shutdown or overcurrent protection event, with VFAULTn of at most 200 mV at 1 mA when asserted. |
| 9 | NC | unconnected | No internal connection on the 20-contact ES,-1 package. |
| 10 | OUT2A | output | DMOS H-bridge 2, output A, driving the bridge 2 motor winding. |
| 11 | SENSE2 | passive | Sense resistor terminal for bridge 2; the SENSEx rating is 0.5 V continuous and 2.5 V pulsed for under 1 µs, and tying it to ground disables internal current limiting. |
| 12 | OUT2B | output | DMOS H-bridge 2, output B, driving the bridge 2 motor winding. |
| 13 | VBB | power_in | Motor supply voltage with an operating range of 2.7 to 15 V and an absolute maximum of 15 V. |
| 14 | OUT1B | output | DMOS H-bridge 1, output B, driving the bridge 1 motor winding. |
| 15 | SENSE1 | passive | Sense resistor terminal for bridge 1; the SENSEx rating is 0.5 V continuous and 2.5 V pulsed for under 1 µs, and tying it to ground disables internal current limiting. |
| 16 | OUT1A | output | DMOS H-bridge 1, output A, driving the bridge 1 motor winding. |
| 17 | VCP | passive | Charge pump capacitor connection, which the application circuit shows with a 0.1 µF capacitor. |
| 18 | NC | unconnected | No internal connection on the 20-contact ES,-1 package. |
| 19 | NC | unconnected | No internal connection on the 20-contact ES,-1 package. |
| 20 | NC | unconnected | No internal connection on the 20-contact ES,-1 package. |
| 21 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | QFN-20-EP(4x4) |
| Category | Motor Driver ICs |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute maximum) | VBB | 15 | V | 2 | |||
| Output Current (absolute maximum) | IOUT | 1 | A | Continuous | 2 | ||
| Output Current, parallel mode (absolute maximum) | IOUT(PAR) | 1.8 | A | Continuous | 2 | ||
| Sense Voltage (absolute maximum) | VSENSEx | 0.5 | V | Continuous | 2 | ||
| Sense Voltage (absolute maximum) | VSENSEx | 2.5 | V | Pulsed, tw < 1 µs | 2 | ||
| Logic Input Voltage Range (absolute maximum) | VIO | -0.3 | 5.5 | V | 2 | ||
| Junction Temperature (absolute maximum) | TJ(MAX) | 150 | °C | 2 | |||
| Storage Temperature Range | Tstg | -55 | 150 | °C | 2 | ||
| Operating Temperature Range | TA | -40 | 105 | °C | Range G | 2 | |
| Load Supply Voltage Range | VBB | 2.7 | 15 | V | Operating | 5 | |
| Output On Resistance, high side | RDS(ON,HS) | 335 | 450 | mΩ | TJ = 25°C, 500 mA, VBB = 5 V | 5 | |
| Output On Resistance, low side | RDS(ON,LS) | 375 | 525 | mΩ | TJ = 25°C, 500 mA, VBB = 5 V | 5 | |
| Diode Forward Voltage | VF | 0.85 | 1 | V | I = 500 mA | 5 | |
| VBB Supply Current, 2.7 V | IBB(2p7V) | 2.2 | 4.5 | mA | Outputs disabled, VBB = 2.7 V | 5 | |
| VBB Supply Current, 15 V | IBB(15V) | 3.1 | 4.5 | mA | Outputs disabled, VBB = 15 V | 5 | |
| VBB Supply Current, sleep mode | IBB(SLEEP) | 0.5 | µA | Sleep Mode | 5 | ||
| Logic Input Voltage, INx high | VIN(1) | 2 | V | 5 | |||
| Logic Input Voltage, INx low | VIN(0) | 0.8 | V | 5 | |||
| Logic Input Voltage, SLEEPn high | VIN(1) | 2 | V | 5 | |||
| Logic Input Voltage, SLEEPn low | VIN(0) | 0.4 | V | 5 | |||
| Logic Input Hysteresis | VHYS | 100 | 500 | mV | 5 | ||
| Logic Input Current | IIN | 33 | 50 | µA | VIN = 3.3 V, pulldown = 100 kΩ | 5 | |
| Fault Output Voltage | VFAULTn | 200 | mV | Flag asserted, IFAULTn = 1 mA | 5 | ||
| Fault Output Leakage Current | IFAULTn | 1 | µA | VFAULTn = 5 V | 5 | ||
| VSENSE Blank time | tBLANK | 2.1 | 3.1 | 4.1 | µs | 5 | |
| VSENSE Trip Voltage | VTRIP | 170 | 205 | 240 | mV | 5 | |
| Fixed Off-Time | tOFF | 20 | 30 | 40 | µs | 5 | |
| Crossover Delay | tOCD | 200 | 550 | 1000 | ns | 5 | |
| VBB Undervoltage Lockout | VBB(UVLO) | 2.55 | 2.65 | V | VBB rising | 5 | |
| Thermal Shutdown Temperature | TJ1 | 150 | 165 | 180 | °C | 5 | |
| VBB Hysteresis | VBB(UVLO,HYS) | 125 | mV | 5 | |||
| Thermal Shutdown Hysteresis | ΔTJ1 | 20 | °C | 5 | |||
| Thermal resistance, junction to ambient, 4 × 4 mm ES-1 package | RθJA | 37 | °C/W | 4-layer PCB based on JEDEC standard | 2 |
CAD (KiCad official)
- Symbol:
A3916GESTR-T-1 - Footprint:
Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm - 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
a3916gestr-t-1-etched.step/a3916gestr-t-1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a3916gestr-t-1.step/a3916gestr-t-1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (11 pp, sha256
50e67b813f034161, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).