# A3909GLYTR-T

**Allegro MicroSystems, LLC** · Gate Drive ICs · MSOP-10-EP

A3909GLYTR-T from Allegro MicroSystems, LLC, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN1 | input | Logic input controlling OUT1/OUT2; logic low is VIL ≤ 0.8 V, high is VIH ≥ 2 V, with a 50 kΩ internal pull-down. |
| 2 | IN2 | input | Logic input controlling OUT1/OUT2; logic low is VIL ≤ 0.8 V, high is VIH ≥ 2 V, with a 50 kΩ internal pull-down. |
| 3 | VBB | power_in | Input supply for the load, operating range 4 to 18 V (absolute maximum 18 V). |
| 4 | IN3 | input | Logic input controlling OUT3/OUT4; logic low is VIL ≤ 0.8 V, high is VIH ≥ 2 V, with a 50 kΩ internal pull-down. |
| 5 | IN4 | input | Logic input controlling OUT3/OUT4; logic low is VIL ≤ 0.8 V, high is VIH ≥ 2 V, with a 50 kΩ internal pull-down. |
| 6 | OUT4 | output | Motor terminal of the second full bridge, rated up to 1 A and -0.3 V to VBB + 1 V. |
| 7 | OUT3 | output | Motor terminal of the second full bridge, rated up to 1 A and -0.3 V to VBB + 1 V. |
| 8 | GND | power_in | Ground reference. |
| 9 | OUT2 | output | Motor terminal of the first full bridge, rated up to 1 A and -0.3 V to VBB + 1 V. |
| 10 | OUT1 | output | Motor terminal of the first full bridge, rated up to 1 A and -0.3 V to VBB + 1 V. |
| 11 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | MSOP-10-EP |
| Category | Power Management ICs |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VBB Voltage Range | VBB | 4 |  | 18 | V |  | 3 |
| VBB Supply Current | IBB |  | 4 | 8 | mA |  | 3 |
| VBB Supply Current Standby Mode | IBB(standby) |  |  | 10 | µA | Standby Mode (typ printed as <1) | 3 |
| Total Driver On-Resistance (Sink + Source) | RDS(on)tot |  | 1.6 | 2 | Ω | I = 1 A, TJ = 25°C, VBB = 12 V | 3 |
| Total Driver On-Resistance (Sink + Source) | RDS(on)tot |  | 2.7 | 3.5 | Ω | I = 1 A, TJ = 25°C, VBB = 4 V | 3 |
| Input Logic Low Level (Standby) | VIL(Standby) |  |  | 0.4 | V | All inputs low | 3 |
| Input Logic Low Level | VIL |  |  | 0.8 | V |  | 3 |
| Input Logic High Level | VIH | 2 |  |  | V |  | 3 |
| Input Hysteresis | VHYS | 100 | 300 | 500 | mV |  | 3 |
| Logic Input Current | IIN |  | 100 | 150 | µA | VIN = 5 V (Pull down = 50 kΩ) | 3 |
| VBB UVLO | VBBUVLO |  | 3.6 | 3.95 | V | VBB rising | 3 |
| VBB UVLO Hysteresis | VBBHYS | 100 | 300 | 500 | mV |  | 3 |
| Standby Timer | tSTB |  | 1 | 1.5 | ms | IN1 = IN2 = IN3 = IN4 < VIL(Standby) | 3 |
| Thermal Shutdown Temperature | TJTSD | 150 | 165 | 180 | °C | Temperature increasing | 3 |
| Supply Voltage | VBB |  |  | 18 | V |  | 2 |
| Logic Input Voltage Range | VIN | -0.3 |  | 6 | V |  | 2 |
| Output Current | IOUT |  |  | 1 | A |  | 2 |
| Output Voltage | VOUT | -0.3 |  |  | V | Upper limit printed as VBB + 1 | 2 |
| Operating Ambient Temperature | TA | -40 |  | 105 | °C | G temperature range | 2 |
| Maximum Junction Temperature | TJ(max) |  |  | 150 | °C |  | 2 |
| Storage Temperature | Tstg | -55 |  | 150 | °C |  | 2 |
| Source Driver On-Resistance | RDS(on)src |  | 1.12 |  | Ω | I = 1 A, TJ = 25°C, VBB = 12 V | 3 |
| Sink Driver On-Resistance | RDS(on)snk |  | 0.48 |  | Ω | I = 1 A, TJ = 25°C, VBB = 12 V | 3 |
| Thermal Shutdown Hysteresis | ΔTJ |  | 20 |  | °C | Recovery = TJTSD, ΔTJ | 3 |
| Package Thermal Resistance LY package | RθJA |  | 48 |  | °C/W | LY package, on 2-layer PCB with 2.260 in.2 of copper area each side | 2 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | wave solder applications. Both packages are lead (Pb) free with 100% matte-tin leadframe plating. | 1 |

## CAD (KiCad official)

- Symbol: `A3909GLYTR-T`
- Footprint: `Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm`
- 3D model: MSOP-10-EP (KiCad packages3D, STEP)
- 3D model files: `a3909glytr-t-etched.step` / `a3909glytr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a3909glytr-t.step` / `a3909glytr-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a3909glytr-t-datasheet.pdf) (10 pp, sha256 `8e1ceccc29a7168e`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a3909glytr-t-datasheet.pdf)