A31315LOLATR-XY-S-AR-10 from Allegro MicroSystems, LLC, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Supply voltage; the datasheet gives a 4.5 to 5.5 V supply operating range, a forward supply voltage absolute maximum of 18 V and a reverse supply voltage of -18 V.
2	NC	unconnected	Not connected; connect to GND for optimal ESD performance.
3	GND	power_in	Ground.
4	OUT	output	Device output in analog ratiometric mode with VCC; forward output voltage absolute maximum is 18 V and reverse output voltage is -6 V, clamped at -10 V to GND.
5	NC	unconnected	Not connected; connect to GND for optimal ESD performance.
6	NC	unconnected	Not connected; connect to GND for optimal ESD performance.
7	NC	unconnected	Not connected; connect to GND for optimal ESD performance.
8	NC	unconnected	Not connected; connect to GND for optimal ESD performance.

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	SOIC-8
Category	Sensors
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage	VCC	4.5	5	5.5	V		8
Supply Buffer Capacitor	CSUP	10	100	600	nF		8
Supply Current	ICC	5	8.5	10	mA	Each die	8
Ambient Operating Temperature	TA	-40		150	°C		8
Number of EEPROM Writes	NEEPROM			100	writes	TA = 25°C	8
Magnetic Flux Density	/BIN/		300	1000	G	For xxx-10 parts, devices tested at /BIN/ = 300 G, operation below this value is characterized, but not specified	8
Undervoltage Detection Threshold	VUVD (LOW, FALL)	3.6		4.1	V	VCC falling, uvd_sel = '0'	9
Undervoltage Detection Threshold	VUVD (LOW, RISE)	3.7		4.2	V	VCC rising, uvd_sel = '0'	9
Undervoltage Detection Threshold	VUVD (HIGH, FALL)	4.1		4.4	V	VCC falling, uvd_sel = '1'	9
Undervoltage Detection Threshold	VUVD (HIGH, RISE)	4.2		4.5	V	VCC rising, uvd_sel = '1'	9
Overvoltage Detection Threshold	VOVD (LOW, FALL)	5.6		6	V	VCC falling, ovd_sel = '1'	9
Overvoltage Detection Threshold	VOVD (LOW, RISE)	5.65		6.05	V	VCC rising, ovd_sel = '1'	9
Overvoltage Detection Threshold	VOVD (HIGH, FALL)	8.4		10.2	V	VCC falling, ovd_sel = '0'	9
Overvoltage Detection Threshold	VOVD (HIGH, RISE)	8.6		10.4	V	VCC rising, ovd_sel = '0'	9
Power-On Reset Voltage	VPOR(FALL)	2.6		2.9	V	VCC falling	9
Power-On Reset Voltage	VPOR(RISE)	2.8		3.1	V	VCC rising	9
Power-On Time	tPO		1	1.7	ms	Time from VCC > VCC(MIN) until unfiltered output is settled	9
Oscillator Frequency	fOSC	7.36	8	8.64	MHz		9
Angle Error (XY)	ERRANG(XY)	-1		1	degrees	TA = 25°C	9
Angle Error (XY)	ERRANG(XY)	-1.2		1.2	degrees	-40 ≤ TA ≤ 150°C	9
Angle Drift (XY)	DRIFTAng,Temp(XY)	-1.2		1.2	degrees	Change in angle relative to TA = 25°C	9
Angle Drift (XY)	DRIFTAng,Life(XY)	-1.3	0.4	1.3	degrees	Change in angle relative to pre-stress conditions	9
Channel Sensitivity Error (X,Y)	ERRSens(X,Y)	-1.5		1.5	%	TA = 25°C	10
Channel Sensitivity Error (X,Y)	ERRSens(X,Y)	-3		3	%	-40 ≤ TA ≤ 150°C	10
Channel Offset Error (X,Y)	ERROff(X,Y)	-1.5		1.5	G	TA = 25°C	10
Channel Offset Error (X,Y)	ERROff(X,Y)	-4		4	G	-40 ≤ TA ≤ 150°C	10
Channel Linearity Error (X,Y)	ERRLin(X,Y)	-0.3		0.3	%	100 G ≤ BIN ≤ 1000 G	10
Channel Sensitivity Error Drift (X,Y)	DRIFTSens,Temp(X,Y)	-2		2	%	Change in sensitivity relative to TA = 25°C	10
Channel Sensitivity Error Drift (X,Y)	DRIFTSens,Life(X,Y)	-2.5	1.3	2.5	%	Change in sensitivity relative to pre-stress conditions	10
Channel Offset Drift (X,Y)	DRIFTOff,Temp(X,Y)	-3.5		3.5	G	Change in offset relative to TA = 25°C	10
Channel Offset Drift (X,Y)	DRIFTOff,Life(X,Y)	-0.9	0.25	0.9	G	Change in offset relative to pre-stress conditions	10
Broken Wire Response Time	tBW			500	µs	Time after VCC, GND = 0.2 V, either VCC or GND wire broken, CL = 100 nF, CSUP = 100 nF	11
High-Z Leakage	Ileak(Hi-Z)	-10		10	µA	Device in High-Z mode, output shorted to GND or VCC	11
Filter Step Response Time	tRESP		396	450	µs	bw_sel = 5, time to 90% response to step	11
DAC DNL	DNL	-0.022		0.022	%VCC	VCC = 5 V	12
DAC INL	INL	-0.098		0.098	%VCC	VCC = 5 V	12
DAC Ratiometry	RAT	-0.2		0.2	%	VOUT = 8 to 92 %VCC	12
DAC Gain Error	GainDAC	-0.2		0.2	%	VCC = 5 V	12
DAC Offset Error	OffDAC	-8		8	mV	VCC = 5 V	12
Saturation Voltage	VSAT(HIGH)	93			%VCC	RL = 4.7 kΩ	12
Saturation Voltage	VSAT(LOW)			7	%VCC	RL = 4.7 kΩ	12
Saturation Voltage	VSAT(HIGH)	95			%VCC	RL = 10 kΩ	12
Saturation Voltage	VSAT(LOW)			5	%VCC	RL = 10 kΩ	12
Operating Voltage Range	VOH	92			%VCC	RL = 4.7 kΩ, linearity error < 0.1 %	12
Operating Voltage Range	VOL			8	%VCC	RL = 4.7 kΩ, linearity error < 0.1 %	12
Operating Voltage Range	VOH	94			%VCC	RL = 10 kΩ, linearity error < 0.1 %	12
Operating Voltage Range	VOL			6	%VCC	RL = 10 kΩ, linearity error < 0.1 %	12
Diagnostic Voltage High	VSATDIAG(HIGH)	94	98	100	%VCC	VCC = 5 V, RL = 3.3 kΩ	12
Diagnostic Voltage High	VSATDIAG(HIGH)	96	98	100	%VCC	VCC = 5 V, RL = 5 kΩ	12
Diagnostic Voltage High	VSATDIAG(HIGH)	97	98	100	%VCC	VCC = 5 V, RL = 10 kΩ	12
Diagnostic Voltage Low	VSATDIAG(LOW)	0	2	6	%VCC	VCC = 5 V, RL = 3.3 kΩ	12
Diagnostic Voltage Low	VSATDIAG(LOW)	0	2	4	%VCC	VCC = 5 V, RL = 5 kΩ	12
Diagnostic Voltage Low	VSATDIAG(LOW)	0	2	3	%VCC	VCC = 5 V, RL = 10 kΩ	12
Load Capacitance	CL	10		150	nF	ana_cap_sel = '0'	13
Load Capacitance	CL	50		480	nF	ana_cap_sel = '2', recommended for CL ≥ 100 nF	13
Load Capacitance	CL	300		600	nF	ana_cap_sel = '4', recommended for CL ≥ 400 nF	13
Load Resistance	RL	4.23			kΩ	Pull-up to VCC or pull-down to GND	13
Analog Response Time	tRESP			600	µs	Sensor output with 100 nF load 1482 Hz bandwidth, time from 90% input change to 90% output change	13
Channel Sensitivity (default target)	SENS		32.125		LSB / G	Target Selection Guide Part Number: XXX-10	10

CAD (KiCad official)

Symbol: A31315LOLATR-XY-S-AR-10
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: a31315lolatr-xy-s-ar-10-etched.step / a31315lolatr-xy-s-ar-10-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a31315lolatr-xy-s-ar-10.step / a31315lolatr-xy-s-ar-10.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (70 pp, sha256 5e17bbddc669f0d8, retrieved 2026-11-02, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A31315LOLATR-XY-S-AR-10

Verified A31315LOLATR-XY-S-AR-10

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README