component
A1392SEHLT-T
Public Made by Adomby adom
Allegro MicroSystems LLC Linear Hall Sensors, DFN-6(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 8d ago |
| viewers | 8d ago |
| a1392sehlt-t-etched.glb | 8d ago |
| a1392sehlt-t-etched.step | 8d ago |
| a1392sehlt-t-hero.glb | 8d ago |
| a1392sehlt-t-hero.overlay.json | 8d ago |
| a1392sehlt-t.glb | 8d ago |
| a1392sehlt-t.kicad_mod | 8d ago |
| a1392sehlt-t.kicad_sym | 8d ago |
| a1392sehlt-t.lbr | 8d ago |
| a1392sehlt-t.step | 8d ago |
| package.json | 8d ago |
| page.json | 8d ago |
| README.md | 8d ago |
A1392SEHLT-T
Allegro MicroSystems LLC · Linear Hall Sensors · DFN-6(2x3)
A1392SEHLT-T from Allegro MicroSystems LLC, in a DFN-6(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply pin with a supply voltage range of 2.5 V to 3.5 V (nominal 3.0 V) and an absolute maximum rating of 8 V; a bypass capacitor should be placed close to the device between VCC and GND. |
| 2 | OUT | output | Linear ratiometric analog output that is high-impedance in sleep mode; it must not be forced more than 0.1 V above VCC and is specified for a load resistance of at least 15 kΩ and load capacitance of at most 10 nF to ground. |
| 3 | GND | power_in | Ground terminal; all device absolute maximum ratings are referenced to ground. |
| 4 | GND | power_in | Second ground terminal, connected to the same ground as pin 3 and used as the VCC-to-GND bypass return. |
| 5 | SLEEP | input | Active-low sleep control: a logic low drives the device into sleep mode (below 25 µA, outputs high-impedance) and a logic high drives it into active mode, with input range −0.1 V to VCC + 0.5 V. |
| 6 | VREF | power_in | Supply for the ratiometric reference, which must be between 2.5 V and VCC; the quiescent output is 50% of the VREF voltage and degraded accuracy occurs below 2.5 V. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | DFN-6(2x3) |
| Category | Magnetic Sensors |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 2.5 | 3.5 | V | 3 | ||
| Supply Zener Clamp Voltage | VCCZ | 6 | 8.3 | V | ICC = 7 mA, TA = 25°C | 3 | |
| Ratiometric Reference Voltage | VREF | 2.5 | V | 3 | |||
| Ratiometric Reference Zener Clamp Voltage | VREFZ | 6 | 8.3 | V | IVREF = 3 mA, TA = 25°C | 3 | |
| SLEEP Input Voltage | -0.1 | V | 3 | ||||
| Ratiometric Reference Input Resistance | RREF | 250 | kΩ | VSLEEP > VINH, VCC = VCCN, TA = 25°C | 3 | ||
| SLEEP Input Current | ISLEEP | -1 | μA | VSLEEP = 3 V, VCC = VCCN | 3 | ||
| Output Load Resistance | RL | 15 | kΩ | Output to ground | 4 | ||
| Output Load Capacitance | CL | 10 | nF | Output to ground | 4 | ||
| Noise (A1392) | Vn | 40 | mVpp | Cbypass = 0.1 μF, no load | 4 | ||
| Power-On Time | tPON | 40 | 60 | μs | 5 | ||
| Supply Voltage (absolute maximum) | VCC | 8 | V | 2 | |||
| Reverse-Supply Voltage | VRCC | -0.1 | V | 2 | |||
| Ratiometric Supply Reference Voltage | VREF | 7 | V | 2 | |||
| Reverse-Ratiometric Supply Reference Voltage | VRREF | -0.1 | V | 2 | |||
| Logic Supply Voltage | VSLEEP | 32 | V | VCC > 2.5 V | 2 | ||
| Reverse-Logic Supply Voltage | VRSLEEP | -0.1 | V | 2 | |||
| Reverse-Output Voltage | VROUT | -0.1 | V | 2 | |||
| Operating Ambient Temperature | TA | -20 | 85 | ºC | Range S | 2 | |
| Junction Temperature | TJ(MAX) | 165 | ºC | 2 | |||
| Storage Temperature | Tstg | -65 | 170 | ºC | 2 | ||
| Package Thermal Resistance | RθJA | 221 | ºC/W | 1-layer PCB with copper limited to solder pads | 8 | ||
| Package Thermal Resistance | RθJA | 70 | ºC/W | 2-layer PCB with 0.6 in.2 of copper area each side, connected by thermal vias | 8 | ||
| Package Thermal Resistance | RθJA | 50 | ºC/W | 4-layer PCB based on JEDEC standard | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | height microleaded package (MLP/DFN). It is Pb (lead) free, with 100% matte tin leadframe plating. | 2 |
CAD (KiCad official)
- Symbol:
A1392SEHLT-T - Footprint:
Package_DFN_QFN:DFN-6-1EP_3x2mm_P0.5mm_EP1.65x1.35mm - 3D model: DFN-6(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
a1392sehlt-t-etched.step/a1392sehlt-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a1392sehlt-t.step/a1392sehlt-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (16 pp, sha256
bb3061cc7b62a316, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).