component
A1391SEHLT-T
Public Made by Adomby adom
Allegro MicroSystems, LLC Magnetic Sensors, DFN-6(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
A1391SEHLT-T
Allegro MicroSystems, LLC · Magnetic Sensors · DFN-6(2x3)
A1391SEHLT-T from Allegro MicroSystems, LLC, in a DFN-6(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply pin, specified for 2.5 to 3.5 V operation with a nominal supply of 3.0 V and an absolute maximum of 8 V. |
| 2 | OUT | output | Linear Hall output that is high-impedance during sleep mode and must not be driven more than 0.1 V above VCC. |
| 3 | GND | power_in | Ground reference for all supply and voltage ratings, which are referenced to ground. |
| 4 | GND | power_in | Ground reference for all supply and voltage ratings, which are referenced to ground. |
| 5 | SLEEP | input | Sleep mode control where a logic low (below 0.20 × VCC) selects sleep mode and a logic high (above 0.45 × VCC) selects active mode, with input voltage limited to -0.1 V to VCC + 0.5 V. |
| 6 | VREF | power_in | Ratiometric reference supply that must be between 2.5 V and VCC, with degraded accuracy below 2.5 V. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | DFN-6(2x3) |
| Category | Sensors |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 2.5 | 3.5 | V | 3 | ||
| Supply Zener Clamp Voltage | VCCZ | 6 | 8.3 | V | ICC = 7 mA, TA = 25°C | 3 | |
| Ratiometric Reference Voltage | VREF | 2.5 | V | 3 | |||
| Ratiometric Reference Zener Clamp Voltage | VREFZ | 6 | 8.3 | V | IVREF = 3 mA, TA = 25°C | 3 | |
| Ratiometric Reference Input Resistance | RREF | 250 | kΩ | VSLEEP > VINH, VCC = VCCN, TA = 25°C | 3 | ||
| SLEEP Input Current | ISLEEP | -1 | μA | VSLEEP = 3 V, VCC = VCCN | 3 | ||
| Output Load Resistance | RL | 15 | kΩ | Output to ground | 4 | ||
| Output Load Capacitance | CL | 10 | nF | Output to ground | 4 | ||
| Noise (A1391) | Vn | 6 | 12 | mVpp | Cbypass = 0.1 μF, BWexternalLPF = 2 kHz | 4 | |
| Noise (A1391) | Vn | 20 | mVpp | Cbypass = 0.1 μF, no load | 4 | ||
| Power-On Time | tPON | 40 | 60 | μs | 5 | ||
| Supply Voltage | VCC | 8 | V | 2 | |||
| Reverse-Supply Voltage | VRCC | -0.1 | V | 2 | |||
| Ratiometric Supply Reference Voltage | VREF | 7 | V | 2 | |||
| Reverse-Ratiometric Supply Reference Voltage | VRREF | -0.1 | V | 2 | |||
| Logic Supply Voltage | 32 | V | VCC > 2.5 V | 2 | |||
| Reverse-Logic Supply Voltage | -0.1 | V | 2 | ||||
| Reverse-Output Voltage | VROUT | -0.1 | V | 2 | |||
| Operating Ambient Temperature | TA | -20 | 85 | ºC | Range S | 2 | |
| Junction Temperature | TJ(MAX) | 165 | ºC | 2 | |||
| Storage Temperature | Tstg | -65 | 170 | ºC | 2 | ||
| Package Thermal Resistance | RθJA | 221 | ºC/W | 1-layer PCB with copper limited to solder pads | 8 | ||
| Package Thermal Resistance | RθJA | 70 | ºC/W | 2-layer PCB with 0.6 in.2 of copper area each side, connected by thermal vias | 8 | ||
| Package Thermal Resistance | RθJA | 50 | ºC/W | 4-layer PCB based on JEDEC standard | 8 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | height microleaded package (MLP/DFN). It is Pb (lead) free, with 100% matte tin leadframe plating. | 2 |
CAD (KiCad official)
- Symbol:
A1391SEHLT-T - Footprint:
Package_DFN_QFN:DFN-6-1EP_3x2mm_P0.5mm_EP1.65x1.35mm - 3D model: DFN-6(2x3) (KiCad packages3D, STEP)
- 3D model files:
a1391sehlt-t-etched.step/a1391sehlt-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a1391sehlt-t.step/a1391sehlt-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems, LLC datasheet (16 pp, sha256
bb3061cc7b62a316, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# A1391SEHLT-T
**Allegro MicroSystems, LLC** · Magnetic Sensors · DFN-6(2x3)
A1391SEHLT-T from Allegro MicroSystems, LLC, in a DFN-6(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Supply pin, specified for 2.5 to 3.5 V operation with a nominal supply of 3.0 V and an absolute maximum of 8 V. |
| 2 | OUT | output | Linear Hall output that is high-impedance during sleep mode and must not be driven more than 0.1 V above VCC. |
| 3 | GND | power_in | Ground reference for all supply and voltage ratings, which are referenced to ground. |
| 4 | GND | power_in | Ground reference for all supply and voltage ratings, which are referenced to ground. |
| 5 | SLEEP | input | Sleep mode control where a logic low (below 0.20 × VCC) selects sleep mode and a logic high (above 0.45 × VCC) selects active mode, with input voltage limited to -0.1 V to VCC + 0.5 V. |
| 6 | VREF | power_in | Ratiometric reference supply that must be between 2.5 V and VCC, with degraded accuracy below 2.5 V. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | DFN-6(2x3) |
| Category | Sensors |
| Pins | 7 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VCC | 2.5 | | 3.5 | V | | 3 |
| Supply Zener Clamp Voltage | VCCZ | 6 | 8.3 | | V | ICC = 7 mA, TA = 25°C | 3 |
| Ratiometric Reference Voltage | VREF | 2.5 | | | V | | 3 |
| Ratiometric Reference Zener Clamp Voltage | VREFZ | 6 | 8.3 | | V | IVREF = 3 mA, TA = 25°C | 3 |
| Ratiometric Reference Input Resistance | RREF | 250 | | | kΩ | VSLEEP > VINH, VCC = VCCN, TA = 25°C | 3 |
| SLEEP Input Current | ISLEEP | -1 | | | μA | VSLEEP = 3 V, VCC = VCCN | 3 |
| Output Load Resistance | RL | 15 | | | kΩ | Output to ground | 4 |
| Output Load Capacitance | CL | | | 10 | nF | Output to ground | 4 |
| Noise (A1391) | Vn | | 6 | 12 | mVpp | Cbypass = 0.1 μF, BWexternalLPF = 2 kHz | 4 |
| Noise (A1391) | Vn | | | 20 | mVpp | Cbypass = 0.1 μF, no load | 4 |
| Power-On Time | tPON | | 40 | 60 | μs | | 5 |
| Supply Voltage | VCC | | | 8 | V | | 2 |
| Reverse-Supply Voltage | VRCC | -0.1 | | | V | | 2 |
| Ratiometric Supply Reference Voltage | VREF | | | 7 | V | | 2 |
| Reverse-Ratiometric Supply Reference Voltage | VRREF | -0.1 | | | V | | 2 |
| Logic Supply Voltage | | | | 32 | V | VCC > 2.5 V | 2 |
| Reverse-Logic Supply Voltage | | -0.1 | | | V | | 2 |
| Reverse-Output Voltage | VROUT | -0.1 | | | V | | 2 |
| Operating Ambient Temperature | TA | -20 | | 85 | ºC | Range S | 2 |
| Junction Temperature | TJ(MAX) | | | 165 | ºC | | 2 |
| Storage Temperature | Tstg | -65 | | 170 | ºC | | 2 |
| Package Thermal Resistance | RθJA | 221 | | | ºC/W | 1-layer PCB with copper limited to solder pads | 8 |
| Package Thermal Resistance | RθJA | 70 | | | ºC/W | 2-layer PCB with 0.6 in.2 of copper area each side, connected by thermal vias | 8 |
| Package Thermal Resistance | RθJA | 50 | | | ºC/W | 4-layer PCB based on JEDEC standard | 8 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | height microleaded package (MLP/DFN). It is Pb (lead) free, with 100% matte tin leadframe plating. | 2 |
## CAD (KiCad official)
- Symbol: `A1391SEHLT-T`
- Footprint: `Package_DFN_QFN:DFN-6-1EP_3x2mm_P0.5mm_EP1.65x1.35mm`
- 3D model: DFN-6(2x3) (KiCad packages3D, STEP)
- 3D model files: `a1391sehlt-t-etched.step` / `a1391sehlt-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a1391sehlt-t.step` / `a1391sehlt-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a1391sehlt-t-datasheet.pdf) (16 pp, sha256 `bb3061cc7b62a316`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/a1391sehlt-t-datasheet.pdf)