# A1363LLUTR-1-T

**Allegro MicroSystems, LLC** · Magnetic Sensors · TSSOP-8

A1363LLUTR-1-T from Allegro MicroSystems, LLC, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin; open-circuit detection on the ground pin (broken wire) is built into the device. |
| 2 | VOUT | output | Analog output signal, also used for programming; the output is clamped and must stay within the stated absolute maximum of 25 V forward and -0.1 V reverse. |
| 3 | NF | passive | No function; do not leave floating, connect to GND. |
| 4 | NF | passive | No function; do not leave floating, connect to GND. |
| 5 | NF | passive | No function; do not leave floating, connect to GND. |
| 6 | NC | unconnected | No connect; leave floating for ideal bandwidth performance. |
| 7 | NC | unconnected | No connect; leave floating for ideal bandwidth performance. |
| 8 | VCC | power_in | Input power supply, operating range 4.5 V to 5.5 V with a bypass capacitor to ground, also used for programming; absolute maximum forward supply voltage is 6 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems, LLC |
| Package | TSSOP-8 |
| Category | Sensors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Forward Supply Voltage | VCC |  |  | 6 | V |  | 3 |
| Reverse Supply Voltage | VRCC | -0.1 |  |  | V |  | 3 |
| Forward Output Voltage | VOUT |  |  | 25 | V |  | 3 |
| Reverse Output Voltage | VROUT | -0.1 |  |  | V |  | 3 |
| Output Source Current | IOUT(source) |  |  | 2.8 | mA | VOUT to GND | 3 |
| Output Sink Current | IOUT(sink) |  |  | 10 | mA | VCC to VOUT | 3 |
| Maximum Number of EEPROM Write Cycles | EEPROMW(max) |  |  | 100 | cycle |  | 3 |
| Operating Ambient Temperature | TA | -40 |  | 150 | °C | L temperature range | 3 |
| Storage Temperature | Tstg | -65 |  | 165 | °C |  | 3 |
| Maximum Junction Temperature | TJ(max) |  |  | 165 | °C |  | 3 |
| ESD Human Body Model | VHBM | -10 |  | 10 | kV | Per AEC-Q100 | 3 |
| ESD Charged Device Model | VCDM | -1 |  | 1 | kV | Per AEC-Q100 | 3 |
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V |  | 4 |
| Supply Current | ICC |  | 10 | 15 | mA | No load on VOUT | 4 |
| Supply Zener Clamp Voltage | Vz | 6.5 | 7.5 |  | V | TA = 25°C, ICC = 30 mA | 4 |
| Output Voltage Clamp High | VCLP(HIGH) | 4.55 |  | 4.85 | V | TA = 25°C, RL(PULLDWN) = 10 kΩ to GND | 4 |
| Output Voltage Clamp Low | VCLP(LOW) | 0.15 |  | 0.45 | V | TA = 25°C, RL(PULLUP) = 10 kΩ to VCC | 4 |
| Output Saturation Voltage High | VSAT(HIGH) | 4.7 |  |  | V | TA = 25°C, RL(PULLDWN) = 10 kΩ to GND | 4 |
| Output Saturation Voltage Low | VSAT(LOW) |  |  | 400 | mV | TA = 25°C, RL(PULLUP) = 10 kΩ to VCC | 4 |
| Output Load Resistance (pull-up) | RL(PULLUP) | 4.7 |  |  | kΩ | VOUT to VCC | 5 |
| Output Load Resistance (pull-down) | RL(PULLDWN) | 4.7 |  |  | kΩ | VOUT to GND | 5 |
| Output Load Capacitance | CL |  | 1 | 10 | nF | VOUT to GND | 5 |
| Initial Unprogrammed Quiescent Voltage Output | VOUT(Q)init | 2.4 | 2.5 | 2.6 | V | TA = 25°C | 5 |
| Quiescent Voltage Output Programming Range | VOUT(Q)PR | 2.3 |  | 2.7 | V | TA = 25°C | 5 |
| Average Quiescent Voltage Output Programming Step Size | StepVOUT(Q) | 1.9 | 2.3 | 2.8 | mV | TA = 25°C | 5 |
| Sensitivity Programming Range (SENS_COARSE = 00) | SensPR | 0.6 |  | 1.3 | mV/G | SENS_COARSE = 00, TA = 25°C | 5 |
| Average Fine Sensitivity Programming Step Size (SENS_COARSE = 00) | StepSENS | 2.4 | 3.2 | 4.1 | µV/G | SENS_COARSE = 00, TA = 25°C | 6 |
| Sensitivity Drift Through Temperature Range | ΔSensTC | -3.5 |  | 3.5 | % | TA = 25°C to 150°C | 6 |
| Quiescent Voltage Output Drift Through Temperature Range | ΔVOUT(Q)TC | -15 |  | 15 | mV | TA = 25°C to 150°C | 6 |
| Quiescent Voltage Output Drift Through Temperature Range | ΔVOUT(Q)TC | -30 |  | 30 | mV | TA = -40°C to 25°C | 6 |
| Linearity Sensitivity Error | LinERR | -1 |  | 1 | % |  | 7 |
| Symmetry Sensitivity Error | SymERR | -1 |  | 1 | % |  | 7 |
| Ratiometry Quiescent Voltage Output Error | RatERRVOUT(Q) | -1 | 0 | 1 | % | Through supply voltage range (relative to VCC = 5 V) | 7 |
| Ratiometry Sensitivity Error | RatERRSens | -2 |  | 2 | % | Through supply voltage range (relative to VCC = 5 V) | 7 |
| Sensitivity Drift Over Lifetime | ΔSensLIFE | -1 |  | 1 | % | TA = 25°C, shift after AEC-Q100 grade 0 qualification testing | 7 |
| Access Code Time Out | tACC |  |  | 8 | ms | Customer Access Code fully entered, measured from VCC crossing VUVLOH | 23 |
| Bit Rate | tBITR | 32 |  | 80 | kbps | Defined by input message bit rate sent from external controller | 23 |
| Bit Time | tBIT | 13.6 | 14.3 | 15 | µs | Data bit pulse width at 70 kbps | 23 |
| Bit Time Error | errTBIT | -11 |  | 11 | % | Deviation in tBIT during one command frame | 23 |
| EEPROM Programming Pulse Setup Time | tsPULSE(E) | 40 |  |  | µs | Delay from last edge of write command to start of EEPROM programming pulse | 23 |
| Manchester Code High Voltage | VMAN(H) | 5.1 |  |  | V | Applied to VCC line | 23 |
| Manchester Code Low Voltage | VMAN(L) |  |  | 3.9 | V | Applied to VCC line | 23 |
| Manchester Code Low Voltage | VMAN(L) |  |  | 0.2 | V | Read from VOUT line | 23 |
| Manchester Level to VCC Delay | tMAN_VCC |  |  | 15 | µs |  | 23 |
| Package Thermal Resistance | RθJA |  | 145 |  | °C/W | LU package, estimated, on 4-layer PCB based on JEDEC standard | 3 |
| Sensitivity Drift Due to Package Hysteresis | ΔSensPKG |  | -1.5 |  | % | TA = 25°C, after temperature cycling, 25°C to 150°C and back to 25°C | 7 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | small outline package, suffix LU) that is lead (Pb) free, with 100% matte tin leadframe plating. | 2 |

## CAD (KiCad official)

- Symbol: `A1363LLUTR-1-T`
- Footprint: `Package_SO:TSSOP-8_4.4x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `a1363llutr-1-t-etched.step` / `a1363llutr-1-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a1363llutr-1-t.step` / `a1363llutr-1-t.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Allegro MicroSystems, LLC datasheet](docs/a1363llutr-1-t-datasheet.pdf) (29 pp, sha256 `88f35a3a8db491c2`, retrieved 2026-11-05, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/a1363llutr-1-t-datasheet.pdf)