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A1333LLETR-T

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Allegro MicroSystems, LLC Position Sensor, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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A1333LLETR-T

Allegro MicroSystems, LLC · Position Sensor · TSSOP-14

A1333LLETR-T from Allegro MicroSystems, LLC, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BYP passive External bypass capacitor terminal for the internal regulator (0.1 µF used in application circuit); also tied to for Manchester ID value '1'.
2 VCC power_in Power supply input (4.0 to 16.5 V operating) and Manchester input.
3 TEST input Test pin; bring to GND.
4 PWM output PWM angle output and Manchester output.
5 GND power_in Device ground terminal (pins 5, 6 and 7 are all ground).
6 GND power_in Device ground terminal (pins 5, 6 and 7 are all ground).
7 GND power_in Device ground terminal (pins 5, 6 and 7 are all ground).
8 CS/SA0 input SPI active-low chip select input; in Manchester mode it is the LSB of the ID value, tied to BYP for '1' or GND for '0'.
9 SCLK input SPI clock input (0.1 to 10 MHz).
10 MOSI/SA1 input SPI master output/slave input; in Manchester mode it is the MSB of the ID value, tied to BYP for '1' or GND for '0'.
11 MISO output SPI master input/slave output.
12 A/U output Option 1: quadrature A output signal; Option 2: U (phase 1) output signal.
13 B/V output Option 1: quadrature B output signal; Option 2: V (phase 2) output signal.
14 I/W output Option 1: quadrature I (index) output signal; Option 2: W (phase 3) output signal.

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package TSSOP-14
Category Sensors
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC 4 16.5 V Customer supply 6
Supply Current ICC 17 19 mA One die, sampling angles 6
Undervoltage Flag Threshold VUVD 3.6 3.9 V dV/dt = 1 V/ms, A1333 sampling enabled, TA = 25°C 6
Supply Zener Clamp Voltage VZSUP 26.5 V ICC = ICC + 3 mA, TA = 25°C 6
Reverse Battery Current IRCC 5 mA VRCC = 18 V, TA = 25°C 6
Power-On Time tPO 15 20 ms Power-on diagnostics disabled 6
Power-on time; CVH self-test and LBIST enabled tPO_D 45 50 ms 6
Bypass Pin Output Voltage VBYP 2.97 3.3 3.63 V TA = 25°C, CBYP = 0.1 µF, 3.3 V interface 6
Digital Input High Voltage VIH 2.8 3.63 V MOSI, SCLK, CS pins 6
Digital Input Low Voltage VIL 0.5 V MOSI, SCLK, CS pins 6
Output High Voltage VOH 2.93 3.3 3.63 V MISO, ABI/UVW pins, CL = 20 pF 6
Output Low Voltage VOL 0.3 V MISO, ABI/UVW pins, CL = 20 pF 6
SPI Clock Frequency fSCLK 0.1 10 MHz MISO pins, CL = 20 pF 6
SPI Clock Duty Cycle DfSCLK 40 60 % SPICLKDC 6
SPI Frame Rate tSPI 5.8 588 kHz 16-bit SPI packet 6
Chip Select to First SCLK Edge tCS 50 ns Time from CS going low to SCLK falling edge 6
Chip Select Idle Time tCS_IDLE 200 ns Time CS must be high between SPI message frames 6
Data Output Valid Time tDAV 30 ns Data output valid after SCLK falling edge 6
MOSI Setup Time tSU 25 ns Input setup time before SCLK rising edge 6
MOSI Hold Time tHD 50 ns Input hold time after SCLK rising edge 6
SCLK to CS Hold Time tCHD 5 ns Hold SCLK high time before CS rising edge 6
Load Capacitance CL 20 pF Loading on digital output (MISO) pin 6
ABI and UVW Output Angular Hysteresis hysANG 0 1.38 degrees Programmable via EEPROM (6 bits) 7
AB Channel Resolution RESAB 1 2048 PPR Programmable via EEPROM, 4 bit field. Specified in pulses per revolution, PPR 7
AB Quadrature Resolution RESAB_INT 4 8192 CPR Equal to 4 × RESAB, specified in counts per revolution, CPR 7
UVW Pole Pairs Npole 1 16 pole pairs DC commutation signals. Programmable via EEPROM, 4-bit field. 7
Manchester High Voltage VMAN(H) 7.3 8 V Applied to VCC line; max printed as VCC(max) 7
Manchester Low Voltage VMAN(L) 5 5.7 V Applied to VCC line; min printed as VCC(min) 7
Manchester Bit Rate fMAN 2.2 100 kbit/s Line state changes once or twice per bit; maximum speed is usually limited by VCC line capacitance 7
Magnetic Field B 1200 G Range of input field 8
Angle Error ERRANG -1 0.4 1 degrees TA = 25°C, ideal magnet alignment, B = 300 G, target rpm = 0 8
Angle Error ERRANG -1.3 0.6 1.3 degrees TA = 150°C, ideal magnet alignment, B = 300 G, target rpm = 0 8
Temperature Drift ANGLEDRIFT -1.4 1.4 degrees TA = 150°C, B = 300 G, angle change from 25°C 8
Forward Supply Voltage VCC 26.5 V Not sampling angles 2
Reverse Supply Voltage VRCC 18 V Not sampling angles 2
All Other Pins Forward Voltage VIN 5.5 V 2
All Other Pins Reverse Voltage VR 0.5 V 2
Operating Ambient Temperature TA -40 150 °C L range 2
Maximum Junction Temperature TJ(max) 170 °C 2
Storage Temperature Tstg -65 170 °C 2
Package Thermal Resistance RθJA 82 °C/W LE-14 package 2
Maximum Operating VCC derating, TSSOP-14 VCC 12.84 V At TA = 144°C, TSSOP-14 Thermal Derating Curve (16.5 V max at lower TA) 8
PWM Carrier Frequency Min Setting fPWM 98 Hz PWM Frequency Min Setting 7
PWM Carrier Frequency Max Setting fPWM 3.125 kHz PWM Frequency Max Setting 7
Angle Noise NANG 0.19 degrees TA = 25°C, B = 300 G, no internal filtering, target rpm = 0, 3 sigma noise (printed ±0.19) 8
Response Time tRESPONSE 7 µs Angular Latency; valid for ABI or UVW interface; ORATE = 0 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin single-die 14-pin TSSOP package. The packages are lead (Pb) free with 100% matte-tin leadframe plating. 1

CAD (KiCad official)

  • Symbol: A1333LLETR-T
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: a1333lletr-t-etched.step / a1333lletr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a1333lletr-t.step / a1333lletr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (87 pp, sha256 fba1b0cba9f11fef, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF