A1318LLHLX-1-T from Allegro MicroSystems, LLC, in a SOT-23W. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VCC	power_in	Input power supply (3 V to 3.63 V operating, 3.3 V typical); tie to GND with a bypass capacitor (0.1 µF used in the datasheet).
2	VOUT	output	Analog ratiometric output signal proportional to the applied magnetic field, with quiescent output of about 1.65 V at 3.3 V supply; requires a load of at least 4.7 kΩ and at most 10 nF to GND.
3	GND	power_in	Ground reference pin.

Key specifications

Parameter	Value
Manufacturer	Allegro MicroSystems, LLC
Package	SOT-23W
Category	Sensors
Pins	3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage	VCC	3	3.3	3.63	V		5
Undervoltage Threshold (power on)	VUVLOHI			3	V	Tested at TA = 25°C and TA = 150°C (device powers on)	5
Undervoltage Threshold (power off)	VUVLOLO	2.5			V	Tested at TA = 25°C and TA = 150°C (device powers off)	5
Supply Current	ICC		7.7	10	mA	No load on VOUT	5
VCC Ramp Time	tVCC	0.005		100	ms	TA = 25°C	5
VCC Off Level	VCCOFF	0		0.33	V	TA = 25°C	5
Supply Zener Clamp Voltage	VZ	6	7.3		V	TA = 25°C, ICC = 13 mA	5
Output Load Resistance	RL	4.7			kΩ	VOUT to GND	5
Output Load Capacitance	CL			10	nF	VOUT to GND	5
Output Voltage Clamp High	VCLPHIGH	2.842	2.97	3.069	V	TA = 25°C, B=+400 G, RL = 10 kΩ (VOUT to GND)	5
Output Voltage Clamp Low	VCLPLOW	0.264	0.33	0.462	V	TA = 25°C, B = -400 G, RL = 10 kΩ (VOUT to VCC)	5
Sensitivity	Sens	1.289	1.35	1.411	mV/G	TA = 25°C	5
Quiescent Voltage Output	VOUT(Q)	1.638	1.65	1.662	V	TA = 25°C	5
Sensitivity Temperature Coefficient	TCSens	0.08	0.12	0.16	%/°C	Programmed at TA = 150°C, calculated relative to Sens at 25°C	6
Typical Quiescent Voltage Output Drift Across Temperature Range	∆VOUT(Q)	-15		5	mV	TA = 150°C	6
Forward Supply Voltage	VCC			8	V		3
Reverse Supply Voltage	VRCC	-0.1			V		3
Forward Output Voltage	VOUT			7	V		3
Reverse Output Voltage	VROUT	-0.1			V		3
Output Source Current	IOUT(SOURCE)			2	mA	VOUT to GND	3
Output Sink Current	IOUT(SINK)			10	mA	VCC to VOUT	3
Operating Ambient Temperature	TA	-40		150	°C	Range L	3
Maximum Junction Temperature	TJ(max)			165	°C		3
Storage Temperature	Tstg	-65		170	°C		3
Package Thermal Resistance (1-layer)	RθJA		228		°C/W	Package LH, 1-layer PCB with copper limited to solder pads	4
Package Thermal Resistance (2-layer)	RθJA		110		°C/W	Package LH, 2-layer PCB with 0.463 in.2 of copper area each side connected by thermal vias	4
Power-On Time	tPO		50		µs	TA = 25°C, CL(PROBE) = 10 pF	5
Delay to Clamp	tCLP		30		µs	TA = 25°C, CL = 10 nF	5
Internal Bandwidth	BWi		20		kHz	Small signal -3 dB	5
Chopping Frequency	fC		400		kHz	TA = 25°C	5
Output Referred Noise	VN		13		mV(p-p)	VCC = 3.3 V, TA = 25°C, CBYPASS = open, Sens = 5 mV/G, no load on VOUT	5
Input Referred RMS Noise Density	VNRMS		2.3		mG/√Hz	VCC = 3.3 V, TA = 25°C, CBYPASS = open, Sens = 5 mV/G, no load on VOUT, fmeasured << BWi	5
Linearity Sensitivity Error	LinERR		1.5		%	printed as ±1.5	6
Symmetry Sensitivity Error	SymERR		1.5		%	printed as ±1.5	6
Ratiometry Quiescent Voltage Output Error	RatVOUT(Q)		1.5		%	Across supply voltage range (relative to VCC = 5 V); printed as ±1.5	6
Ratiometry Sensitivity Error	RatSens		1.5		%	Across supply voltage range (relative to VCC = 5 V); printed as ±1.5	6
Ratiometry Clamp Error	RatVOUTCLP		1.5		%	TA = 25°C, across supply voltage range (relative to VCC = 5 V); printed as ±1.5	6
Sensitivity Drift Due to Package Hysteresis	∆SensPKG		2		%	TA = 25°C, after temperature cycling; printed as ±2	6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	lead (Pb) free, with 100% matte-tin leadframe plating. SELECTION GUIDE	3

CAD (KiCad official)

Symbol: A1318LLHLX-1-T
Footprint: Package_TO_SOT_SMD:SOT-23
3D model: SOT-23W (KiCad packages3D, STEP)
3D model files: a1318llhlx-1-t-etched.step / a1318llhlx-1-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a1318llhlx-1-t.step / a1318llhlx-1-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Allegro MicroSystems, LLC datasheet (13 pp, sha256 a1acba869cadd9a5, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

A1318LLHLX-1-T

Verified A1318LLHLX-1-T

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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