component
9ZXL0853EKILF
Public Made by Adomby adom
RENESAS Clock Buffers, Drivers, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "9zxl0853ekilf",
"version": "0.1.0",
"type": "component",
"description": "RENESAS Clock Buffers, Drivers, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"clock and timing",
"9zxl0853ekilf",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"9zxl0853ekilf.kicad_sym",
"9zxl0853ekilf.kicad_mod",
"9zxl0853ekilf.glb",
"9zxl0853ekilf.step",
"9zxl0853ekilf.lbr",
"docs/hero.png",
"docs/9zxl0853ekilf-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"9zxl0853ekilf-hero.glb",
"9zxl0853ekilf-hero.overlay.json",
"9zxl0853ekilf-etched.glb"
],
"component": {
"mpn": "9ZXL0853EKILF",
"manufacturer": "RENESAS",
"package": "QFN-48-EP(6x6)",
"pin_count": 49,
"category": "Clock and Timing",
"subcategory": "Clock Buffers, Drivers",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/660ca2564c39cbe222df0a5708596af6.pdf",
"parts": {
"symbol": "9zxl0853ekilf.kicad_sym",
"footprint": "9zxl0853ekilf.kicad_mod",
"model_3d": "9zxl0853ekilf-hero.glb",
"model_3d_plain": "9zxl0853ekilf-etched.glb",
"model_3d_step": "9zxl0853ekilf-etched.step",
"model_3d_step_plain": "9zxl0853ekilf.step",
"lbr": "9zxl0853ekilf.lbr"
},
"distributor_links": {
"lcsc": "C1018153",
"digikey": "6690-9ZXL0853EKILF-ND",
"mouser": "972-9ZXL0853EKILF"
},
"distributor_check": {
"checked_at": "2026-10-30T21:58:46Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "6690-9ZXL0853EKILF-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "972-9ZXL0853EKILF",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "^CKPWRGD_PD#",
"type": "input",
"description": "Input notifies the device to sample the latched inputs and start up on the first high assertion; low enters Power Down Mode and subsequent high assertions exit it; internal pull-up."
},
{
"number": "2",
"name": "VDDR",
"type": "power_in",
"description": "Power supply for the differential input clock receiver, to be treated as an analog rail and filtered appropriately; nominally 3.3V."
},
{
"number": "3",
"name": "DIF_IN",
"type": "input",
"description": "HCSL true differential clock input."
},
{
"number": "4",
"name": "DIF_IN#",
"type": "input",
"description": "HCSL complementary differential clock input."
},
{
"number": "5",
"name": "vSADR0_tri",
"type": "input",
"description": "Tri-level SMBus address bit that works with vSADR1_tri to decode SMBus addresses; internal pull-down."
},
{
"number": "6",
"name": "SMBDAT",
"type": "bidirectional",
"description": "Data pin of the SMBus circuitry."
},
{
"number": "7",
"name": "SMBCLK",
"type": "input",
"description": "Clock pin of the SMBus circuitry."
},
{
"number": "8",
"name": "vSADR1_tri",
"type": "input",
"description": "Tri-level SMBus address bit that works with vSADR0_tri to decode SMBus addresses; internal pull-down."
},
{
"number": "9",
"name": "FBOUT_NC#",
"type": "output",
"description": "Complementary half of the differential feedback output; this pin should NOT be connected to anything outside the chip."
},
{
"number": "10",
"name": "FBOUT_NC",
"type": "output",
"description": "True half of the differential feedback output; this pin should NOT be connected to anything outside the chip."
},
{
"number": "11",
"name": "VDD",
"type": "power_in",
"description": "Power supply, nominally 3.3V."
},
{
"number": "12",
"name": "vOE0#",
"type": "input",
"description": "Active-low output enable for output 0 (1 = disable output, 0 = enable output); internal pull-down."
},
{
"number": "13",
"name": "DIF0",
"type": "output",
"description": "Differential true clock output 0."
},
{
"number": "14",
"name": "DIF0#",
"type": "output",
"description": "Differential complementary clock output 0."
},
{
"number": "15",
"name": "VDD",
"type": "power_in",
"description": "Power supply, nominally 3.3V."
},
{
"number": "16",
"name": "DIF1",
"type": "output",
"description": "Differential true clock output 1."
},
{
"number": "17",
"name": "DIF1#",
"type": "output",
"description": "Differential complementary clock output 1."
},
{
"number": "18",
"name": "vOE1#",
"type": "input",
"description": "Active-low output enable for output 1 (1 = disable output, 0 = enable output); internal pull-down."
},
{
"number": "19",
"name": "VDD",
"type": "power_in",
"description": "Power supply, nominally 3.3V."
},
{
"number": "20",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "21",
"name": "DIF2",
"type": "output",
"description": "Differential true clock output 2."
},
{
"number": "22",
"name": "DIF2#",
"type": "output",
"description": "Differential complementary clock output 2."
},
{
"number": "23",
"name": "vOE2#",
"type": "input",
"description": "Active-low output enable for output 2 (1 = disable output, 0 = enable output); internal pull-down."
},
{
"number": "24",
"name": "vOE3#",
"type": "input",
"description": "Active-low output enable for output 3 (1 = disable output, 0 = enable output); internal pull-down."
},
{
"number": "25",
"name": "DIF3",
"type": "output",
"description": "Differential true clock output 3."
},
{
"number": "26",
"name": "DIF3#",
"type": "output",
"description": "Differential complementary clock output 3."
},
{
"number": "27",
"name": "VDD",
"type": "power_in",
"description": "Power supply, nominally 3.3V."
},
{
"number": "28",
"name": "DIF4",
"type": "output",
"description": "Differential true clock output 4."
},
{
"number": "29",
"name": "DIF4#",
"type": "output",
"description": "Differential complementary clock output 4."
},
{
"number": "30",
"name": "vOE4#",
"type": "input",
"description": "Active-low output enable for output 4 (1 = disable output, 0 = enable output); internal pull-down."
},
{
"number": "31",
"name": "vOE5#",
"type": "input",
"description": "Active-low output enable for output 5 (1 = disable output, 0 = enable output); internal pull-down."
},
{
"number": "32",
"name": "DIF5",
"type": "output",
"description": "Differential true clock output 5."
},
{
"number": "33",
"name": "DIF5#",
"type": "output",
"description": "Differential complementary clock output 5."
},
{
"number": "34",
"name": "VDD",
"type": "power_in",
"description": "Power supply, nominally 3.3V."
},
{
"number": "35",
"name": "DIF6",
"type": "output",
"description": "Differential true clock output 6."
},
{
"number": "36",
"name": "DIF6#",
"type": "output",
"description": "Differential complementary clock output 6."
},
{
"number": "37",
"name": "vOE6#",
"type": "input",
"description": "Active-low output enable for output 6 (1 = disable output, 0 = enable output); internal pull-down."
},
{
"number": "38",
"name": "VDD",
"type": "power_in",
"description": "Power supply, nominally 3.3V."
},
{
"number": "39",
"name": "DIF7",
"type": "output",
"description": "Differential true clock output 7."
},
{
"number": "40",
"name": "DIF7#",
"type": "output",
"description": "Differential complementary clock output 7."
},
{
"number": "41",
"name": "vOE7#",
"type": "input",
"description": "Active-low output enable for output 7 (1 = disable output, 0 = enable output); internal pull-down."
},
{
"number": "42",
"name": "VDD",
"type": "power_in",
"description": "Power supply, nominally 3.3V."
},
{
"number": "43",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "44",
"name": "VDDA",
"type": "power_in",
"description": "Power supply for the PLL core."
},
{
"number": "45",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "46",
"name": "vSMB_WRTLOCK",
"type": "input",
"description": "When asserted (1) it blocks SMBus writes while SMBus reads are unaffected (0 = writes allowed); internal pull-down."
},
{
"number": "47",
"name": "^100M_133M#",
"type": "input",
"description": "3.3V latched input selecting the operating frequency; internal pull-up."
},
{
"number": "48",
"name": "^HIBW_BYPM_LOBW#",
"type": "input",
"description": "Tri-level latched input selecting High BW, Bypass or Low BW PLL mode; internal pull-up."
},
{
"number": "49",
"name": "EPAD",
"type": "power_in",
"description": "Exposed pad; connect to ground. Table 1 assigns GNDA (PLL core ground) and GNDR (receiver analog ground) to this pad for the 9ZXL0853."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pinout taken from the 9ZXL0853E 48-VFQFPN pin assignment figure (page 5), cross-checked against the ; The 9ZXL0853 has no separate ground pins other than the exposed pad (pin 49). GNDA and GNDR are both; The NC row in Table 1 is garbled in the text extraction. NC pins 20, 43 and 45 were taken from the 9"
],
"pages_sent": 15,
"cost_usd": 0.1041,
"at": "2026-10-30T21:58:24"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/660ca2564c39cbe222df0a5708596af6.pdf",
"pages": 36,
"sha256": "f367280c3d8612c9",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 49,
"described": 49,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "9zxl0853ekilf.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.02,
6.02,
0.9
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "a42d074079843fd9157a3db6451b10203cd1bcb71694c41c81ec72d0936d27b0",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "9zxl0853ekilf-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.02,
6.02,
0.9
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "308ac062cae77472467014c2732cfb3f4a187ec995a371b85cf4c66bdbda8372",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}