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9ZXL0853EKILF

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RENESAS Clock Buffers, Drivers, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing9zxl0853ekilffactory-2.0.0extractor-text

Verified 9ZXL0853EKILF

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 9ZXL0853EKILF · QFN-48-EP(6x6) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 36-page datasheet
  • ✓distributor: lcsc C1018153, digikey 6690-9ZXL0853EKILF-ND, mouser 972-9ZXL0853EKILF
  • ✓family: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-g43iw0qt/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 9zxl0853ekilf.kicad_sym✓ 9zxl0853ekilf.kicad_mod✓ 9zxl0853ekilf.step
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Ray Publish 0.1.0 a57a3b0 3d ago

9ZXL0853EKILF

RENESAS · Clock Buffers, Drivers · QFN-48-EP(6x6)

9ZXL0853EKILF from RENESAS, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ^CKPWRGD_PD# input Input notifies the device to sample the latched inputs and start up on the first high assertion; low enters Power Down Mode and subsequent high assertions exit it; internal pull-up.
2 VDDR power_in Power supply for the differential input clock receiver, to be treated as an analog rail and filtered appropriately; nominally 3.3V.
3 DIF_IN input HCSL true differential clock input.
4 DIF_IN# input HCSL complementary differential clock input.
5 vSADR0_tri input Tri-level SMBus address bit that works with vSADR1_tri to decode SMBus addresses; internal pull-down.
6 SMBDAT bidirectional Data pin of the SMBus circuitry.
7 SMBCLK input Clock pin of the SMBus circuitry.
8 vSADR1_tri input Tri-level SMBus address bit that works with vSADR0_tri to decode SMBus addresses; internal pull-down.
9 FBOUT_NC# output Complementary half of the differential feedback output; this pin should NOT be connected to anything outside the chip.
10 FBOUT_NC output True half of the differential feedback output; this pin should NOT be connected to anything outside the chip.
11 VDD power_in Power supply, nominally 3.3V.
12 vOE0# input Active-low output enable for output 0 (1 = disable output, 0 = enable output); internal pull-down.
13 DIF0 output Differential true clock output 0.
14 DIF0# output Differential complementary clock output 0.
15 VDD power_in Power supply, nominally 3.3V.
16 DIF1 output Differential true clock output 1.
17 DIF1# output Differential complementary clock output 1.
18 vOE1# input Active-low output enable for output 1 (1 = disable output, 0 = enable output); internal pull-down.
19 VDD power_in Power supply, nominally 3.3V.
20 NC unconnected No connect.
21 DIF2 output Differential true clock output 2.
22 DIF2# output Differential complementary clock output 2.
23 vOE2# input Active-low output enable for output 2 (1 = disable output, 0 = enable output); internal pull-down.
24 vOE3# input Active-low output enable for output 3 (1 = disable output, 0 = enable output); internal pull-down.
25 DIF3 output Differential true clock output 3.
26 DIF3# output Differential complementary clock output 3.
27 VDD power_in Power supply, nominally 3.3V.
28 DIF4 output Differential true clock output 4.
29 DIF4# output Differential complementary clock output 4.
30 vOE4# input Active-low output enable for output 4 (1 = disable output, 0 = enable output); internal pull-down.
31 vOE5# input Active-low output enable for output 5 (1 = disable output, 0 = enable output); internal pull-down.
32 DIF5 output Differential true clock output 5.
33 DIF5# output Differential complementary clock output 5.
34 VDD power_in Power supply, nominally 3.3V.
35 DIF6 output Differential true clock output 6.
36 DIF6# output Differential complementary clock output 6.
37 vOE6# input Active-low output enable for output 6 (1 = disable output, 0 = enable output); internal pull-down.
38 VDD power_in Power supply, nominally 3.3V.
39 DIF7 output Differential true clock output 7.
40 DIF7# output Differential complementary clock output 7.
41 vOE7# input Active-low output enable for output 7 (1 = disable output, 0 = enable output); internal pull-down.
42 VDD power_in Power supply, nominally 3.3V.
43 NC unconnected No connect.
44 VDDA power_in Power supply for the PLL core.
45 NC unconnected No connect.
46 vSMB_WRTLOCK input When asserted (1) it blocks SMBus writes while SMBus reads are unaffected (0 = writes allowed); internal pull-down.
47 ^100M_133M# input 3.3V latched input selecting the operating frequency; internal pull-up.
48 ^HIBW_BYPM_LOBW# input Tri-level latched input selecting High BW, Bypass or Low BW PLL mode; internal pull-up.
49 EPAD power_in Exposed pad; connect to ground. Table 1 assigns GNDA (PLL core ground) and GNDR (receiver analog ground) to this pad for the 9ZXL0853.

Key specifications

Parameter Value
Manufacturer RENESAS
Package QFN-48-EP(6x6)
Category Clock and Timing
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDx 3.9 V 10
Input High Voltage (SMBus clock and data pins) VIHSMB 3.9 V SMBus clock and data pins 10
Storage Temperature Ts -65 150 °C 10
Junction Temperature Tj 125 °C 10
Input ESD Protection ESD prot 2500 V Human Body Model 10
Thermal Resistance Junction to Case (NDG48) θJC 19 °C/W Junction to case 10
Thermal Resistance Junction to Air, still air (NDG48) θJA0 30 °C/W Junction to air, still air 10
Thermal Resistance Junction to Air, 1 m/s air flow (NDG48) θJA1 23 °C/W Junction to air, 1 m/s air flow 10
Thermal Resistance Junction to Air, 3 m/s air flow (NDG48) θJA3 20 °C/W Junction to air, 3 m/s air flow 10
SMBus Input Low Voltage VILSMB 0.8 V 11
SMBus Input High Voltage VIHSMB 2.1 V 11
SMBus Output Low Voltage VOLSMB 0.4 V At IPULLUP 11
SMBus Sink Current IPULLUP 4 mA At VOL 11
Nominal Bus Voltage VDDSMB 2.7 3.6 V 11
SCLK/SDATA Rise Time tRSMB 1000 ns (Max VIL - 0.15V) to (Min VIH + 0.15V) 11
SCLK/SDATA Fall Time tFSMB 300 ns (Min VIH + 0.15V) to (Max VIL - 0.15V) 11
SMBus Operating Frequency fSMB 400 kHz SMBus operating frequency 11
Input Crossover Voltage, DIF_IN VCROSS 150 900 mV Crossover voltage 11
Input Swing, DIF_IN VSWING 300 mV Differential value 11
Input Slew Rate, DIF_IN dv/dt 0.4 8 V/ns Measured differentially 11
Input Duty Cycle dtin 45 55 % Measurement from differential waveform 11
Input Jitter, Cycle to Cycle, DIF_IN JDIFIn 0 125 ps Differential measurement 11
Supply Voltage VDDx 3.135 3.3 3.465 V 12
Output Supply Voltage VDDIO 0.95 1.05 3.465 V 12
Ambient Operating Temperature (Industrial range) TAMB -40 25 85 °C Industrial range (TIND) 12
Input High Voltage (single-ended) VIH 2 V Single-ended inputs, except SMBus, tri-level inputs 12
Input Low Voltage (single-ended) VIL 0.8 V Single-ended inputs, except SMBus, tri-level inputs 12
Input High Voltage (tri-level) VIH 2.2 V Tri-level inputs 12
Input Mid Voltage (tri-level) VIM 1.2 1.8 V Tri-level inputs 12
Input Low Voltage (tri-level) VIL 0.8 V Tri-level inputs 12
Input Current IIN -5 5 μA Single-ended inputs, VIN = GND, VIN = VDD 12
Input Current (inputs with internal pull resistors) IINP -50 50 μA Single-ended inputs; VIN = 0 V with internal pull-up; VIN = VDD with internal pull-down 12
Input Frequency (Bypass Mode) Fibyp 1 400 MHz VDD = 3.3V, Bypass Mode 12
Input Frequency (100MHz PLL Mode) Fipll 98.5 100 102.5 MHz VDD = 3.3V, 100MHz PLL Mode 12
Input Capacitance (logic inputs, except DIF_IN) CIN 1.5 5 pF Logic inputs, except DIF_IN 12
Clk Stabilization TSTAB 1 1.8 ms From VDD power-up and after input clock stabilization or deassertion of PD# to 1st clock 12
OE# Latency tLATOE# 4 5 10 clocks DIF start after OE# assertion; DIF stop after OE# deassertion 12
Tdrive_PD# tDRVPD 49 300 μs DIF output enable after PD# deassertion 12
Operating Supply Current, VDDA, PLL Mode at 100MHz (9ZXL08) IDDA 37 45 mA VDDA, PLL Mode at 100MHz 13
Operating Supply Current, VDDA, Fanout Buffer Mode at 100MHz (9ZXL08) IDDA 4 5 mA VDDA, Fanout Buffer Mode at 100MHz 13
Operating Supply Current, all other VDD pins at 100MHz (9ZXL08) IDD 55 68 mA All other VDD pins at 100MHz 13
Power Down Current, VDDA (9ZXL08) IDDAPD 3 4 mA VDDA, CKPWRGD_PD# = 0 13
Power Down Current, all other VDD pins (9ZXL08) IDDPD 1 2 mA All other VDD pins, CKPWRGD_PD# = 0 13
Input-to-output skew in PLL Mode tSPO_PLL -100 -21.3 100 ps PLL Mode at 100MHz, nominal temperature and voltage 14
Input-to-output skew in Bypass Mode tPD_BYP 2 2.6 3 ns Bypass Mode at 100MHz, nominal temperature and voltage 14
Input-to-output skew variation in PLL Mode tDSPO_PLL -50 0 50 ps PLL Mode at 100MHz, across voltage and temperature 14
Input-to-output skew variation in Bypass Mode tDSPO_BYP -350 350 ps Bypass Mode at 100MHz, across voltage and temperature, TAMB = -40°C to +85°C 14
Output-to-output skew across all outputs tSKEW_ALL 50 ps Common to PLL and Bypass Mode, at 100MHz 14
PLL Jitter Peaking (high BW) jpeak-hibw 0 1.3 2.5 dB LOBW#_BYPASS_HIBW = 1 14
PLL Jitter Peaking (low BW) jpeak-lobw 0 1.3 2 dB LOBW#_BYPASS_HIBW = 0 14
PLL Bandwidth (high BW) pllHIBW 2 2.6 4 MHz LOBW#_BYPASS_HIBW = 1 14
PLL Bandwidth (low BW) pllLOBW 0.7 1 1.4 MHz LOBW#_BYPASS_HIBW = 0 14
Duty Cycle tDC 45 50.3 55 % Measured differentially, PLL Mode 14
Duty Cycle Distortion tDCD -1 0 1 % Measured differentially, Bypass Mode at 100MHz 14
Jitter, Cycle to Cycle tjcyc-cyc 14 50 ps PLL Mode 14
Slew Rate dV/dt 2 2.9 4 V/ns Scope averaging on 15
Maximum Voltage (LP-HCSL) Vmax 700 792 850 mV Single-ended signal using absolute value (scope averaging off) 15
Minimum Voltage (LP-HCSL) Vmin -150 -35 150 mV 15
Crossing Voltage (abs) (LP-HCSL) Vcross_abs 300 372 462 mV Scope averaging off 15
Crossing Voltage (var) (LP-HCSL) Δ-Vcross 15 50 140 mV Scope averaging off 15

CAD (KiCad official)

  • Symbol: 9ZXL0853EKILF
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 9zxl0853ekilf-etched.step / 9zxl0853ekilf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 9zxl0853ekilf.step / 9zxl0853ekilf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (36 pp, sha256 f367280c3d8612c9, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF