component

9FGV0241AKILF

Public Made by Adom

by adom

RENESAS Clock Generators / Frequency Synthesizers / PLL, QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timing9fgv0241akilffactory-2.0.0extractor-text

Verified 9FGV0241AKILF

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier lcsc, 25 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 9FGV0241AKILF · QFN-24(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 17-page datasheet
  • ✓distributor: lcsc C1527285, digikey 6690-9FGV0241AKILF-ND, mouser 972-9FGV0241AKILF
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9zii6zov/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 9fgv0241akilf.kicad_sym✓ 9fgv0241akilf.kicad_mod✓ 9fgv0241akilf.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 12h ago
viewers 9fgv0241akilf: viewers · Ray 12h ago
9fgv0241akilf-etched.glb Publish 0.1.0 · Ray 12h ago
9fgv0241akilf-etched.step 9fgv0241akilf: factory component page (tier=lcsc) · Ray 12h ago
9fgv0241akilf-hero.glb 9fgv0241akilf: hero GLB from the etched model (keeps the MPN mark) · Ray 12h ago
9fgv0241akilf-hero.overlay.json Publish 0.1.0 · Ray 12h ago
9fgv0241akilf.glb Publish 0.1.0 · Ray 12h ago
9fgv0241akilf.kicad_mod Publish 0.1.0 · Ray 12h ago
9fgv0241akilf.kicad_sym Publish 0.1.0 · Ray 12h ago
9fgv0241akilf.lbr Publish 0.1.0 · Ray 12h ago
9fgv0241akilf.step Publish 0.1.0 · Ray 12h ago
package.json Publish 0.1.0 · Ray 12h ago
page.json Set visibility: public · Ray 12h ago
README.md Publish 0.1.0 · Ray 12h ago
verification.json Verified: Published by the parts factory: tier lcsc, 25 pins · Ray 12h ago

9FGV0241AKILF

RENESAS · Clock Generators / Frequency Synthesizers / PLL · QFN-24(4x4)

9FGV0241AKILF from RENESAS, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 X1_25 input Crystal input, nominally 25.00MHz.
2 X2 output Crystal output; it should be left floating when X1 is driven by an external oscillator.
3 VDDXTAL1.8 power_in Power supply for XTAL, nominal 1.8V.
4 vSADR/REF1.8 bidirectional Latch that selects the SMBus address, and a 1.8V LVCMOS copy of the X1 pin.
5 GNDREF power_in Ground pin for the REF outputs.
6 GNDDIG power_in Ground pin for digital circuitry.
7 VDDDIG1.8 power_in 1.8V digital power (dirty power).
8 SCLK_3.3 input Clock pin of SMBus circuitry, 3.3V tolerant.
9 SDATA_3.3 bidirectional Data pin for SMBus circuitry, 3.3V tolerant.
10 GND power_in Ground pin.
11 VDD1.8 power_in Power supply, nominal 1.8V.
12 vOE0# input Active low input enabling DIF pair 0, with an internal pull-down: 1 disables outputs, 0 enables outputs.
13 DIF0 output Differential true clock output.
14 DIF0# output Differential complementary clock output.
15 GNDA power_in Ground pin for the PLL core.
16 VDDA1.8 power_in 1.8V power for the PLL core.
17 DIF1 output Differential true clock output.
18 DIF1# output Differential complementary clock output.
19 vOE1# input Active low input enabling DIF pair 1, with an internal pull-down: 1 disables outputs, 0 enables outputs.
20 VDD1.8 power_in Power supply, nominal 1.8V.
21 GND power_in Ground pin.
22 ^CKPWRGD_PD# input Notifies the device to sample latched inputs and start up on first high assertion; low enters power down mode and later high assertions exit it, with an internal pull-up.
23 vSS_EN_tri power_in Latched select for spread spectrum amount at initial power up: 1 = -0.5%, M = -0.25%, 0 = spread off.
24 GNDXTAL power_in Ground for XTAL.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer RENESAS
Package QFN-24(4x4)
Category Clock and Timing
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
1.8V Supply Voltage VDDxx -0.5 2.5 V Applies to All VDD pins 5
Input High Voltage, SMBus VIHSMB 3.6 V SMBus clock and data pins 5
Storage Temperature Ts -65 150 °C 5
Junction Temperature Tj 125 °C 5
Operating Supply Current, PLL mode IDDAOP 7 8 mA VDDA, PLL Mode, All outputs active @100MHz 5
Operating Supply Current IDDOP 15 18 mA VDD, All outputs active @100MHz 5
Suspend Supply Current IDDSUSP 6 8 mA VDDxxx, PD# = 0, Wake-On-LAN enabled 5
Powerdown Current IDDPD 0.6 1 mA PD#=0 5
Duty Cycle tDC 45 50 55 % Measured differentially, PLL Mode 5
Skew, Output to Output tsk3 34 50 ps VT = 50% 5
Jitter, Cycle to cycle tjcyc-cyc 14 50 ps PLL mode 5
1.8V Supply Voltage VDD 1.7 1.8 1.9 V Supply voltage for core, analog and single-ended LVCMOS outputs 6
Industrial Ambient Operating Temperature TIND -40 25 85 °C Industrial range 6
Output Low Voltage VIL 0.45 V Single-ended outputs, except SMBus. IOL = -2mA 6
Input Current IIN -5 5 uA Single-ended inputs, VIN = GND, VIN = VDD 6
Input Current with internal pull resistors IINP -20 20 uA Single-ended inputs; VIN = 0 V for inputs with internal pull-up resistors; VIN = VDD for inputs with internal pull-down resistors 6
Input Frequency Fin 23 25 27 MHz XTAL, or X1 input 6
Pin Inductance Lpin 7 nH 6
Input Capacitance CIN 1.5 5 pF Logic Inputs, except DIF_IN 6
Output Pin Capacitance COUT 6 pF Output pin capacitance 6
Clk Stabilization TSTAB 0.4 1.8 ms From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock 6
SS Modulation Frequency fMOD 31 31.6 32 kHz Allowable Frequency (Triangular Modulation) 6
OE# Latency tLATOE# 2 3 4 clocks DIF start after OE# assertion; DIF stop after OE# deassertion 6
Tdrive_PD# tDRVPD 4 300 us DIF output enable after PD# de-assertion 6
Tfall tF 5 ns Fall time of single-ended control inputs 6
Trise tR 5 ns Rise time of single-ended control inputs 6
SMBus Input Low Voltage VILSMB 0.8 V VDDSMB = 3.3V 6
SMBus Input High Voltage VIHSMB 2.1 3.6 V VDDSMB = 3.3V 6
SMBus Output Low Voltage VOLSMB 0.4 V @ IPULLUP 6
Nominal Bus Voltage VDDSMB 1.7 3.6 V 6
SCLK/SDATA Rise Time tRSMB 1000 ns (Max VIL - 0.15) to (Min VIH + 0.15) 6
SCLK/SDATA Fall Time tFSMB 300 ns (Min VIH + 0.15) to (Max VIL - 0.15) 6
SMBus Operating Frequency fMAXSMB 400 kHz Maximum SMBus operating frequency 6
Slew Rate, scope averaging on 3.0V/ns setting 2 3.1 4.3 V/ns Scope averaging on 3.0V/ns setting 7
Slew Rate, scope averaging on 2.0V/ns setting 1.5 2.3 3.5 V/ns Scope averaging on 2.0V/ns setting 7
Slew rate matching ΔTrf 3 20 % Slew rate matching, Scope averaging on 7
Voltage High VHIGH 660 794 850 mV 7
Voltage Low VLOW -150 21 150 mV 7
Max Voltage Vmax 816 1150 mV 7
Min Voltage Vmin -300 -15 mV 7
Vswing Vswing 300 1551 mV Scope averaging off 7
Crossing Voltage (abs) Vcross_abs 300 397 550 mV Scope averaging off 7
Crossing Voltage (var) Δ-Vcross 15 140 mV Scope averaging off 7
Phase Jitter PCIe Gen 1 tjphPCIeG1-CC 21 25 35 ps (p-p) PCIe Gen 1, PLL mode 7
Phase Jitter PCIe Gen 2 Low Band tjphPCIeG2-CC 0.9 0.9 1.1 ps (rms) PCIe Gen 2 Low Band, 10kHz < f < 1.5MHz 7
Phase Jitter PCIe Gen 2 High Band tjphPCIeG2-CC 1.5 1.6 1.9 ps (rms) PCIe Gen 2 High Band, 1.5MHz < f < Nyquist (50MHz) 7
Phase Jitter PCIe Gen 3 tjphPCIeG3-CC 0.3 0.37 0.44 ps (rms) PCIe Gen 3, PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz 7
Phase Jitter PCIe Gen 4 tjphPCIeG4-CC 0.3 0.37 0.44 ps (rms) PCIe Gen 4, PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz 7
Rise/Fall Slew Rate Byte 3 = 1F trf1 0.5 1 2.5 V/ns Byte 3 = 1F, VOH = VDD-0.45V, VOL = 0.45V 8
Rise/Fall Slew Rate Byte 3 = 9F trf1 0.5 2 2.5 V/ns Byte 3 = 9F, VOH = VDD-0.45V, VOL = 0.45V 8
Rise/Fall Slew Rate Byte 3 = DF trf1 0.5 2.1 2.5 V/ns Byte 3 = DF, VOH = VDD-0.45V, VOL = 0.45V 8
Duty Cycle dt1 45 53.1 55 % VT = VDD/2 V 8
Duty Cycle Distortion dtcd 0 2 4 % VT = VDD/2 V 8
Jitter, cycle to cycle tjcyc-cyc 19 250 ps VT = VDD/2 V 8
Jitter, phase tjphREF 0.63 1.5 ps (rms) 12kHz to 5MHz 8
Junction to Case θJC 62 °C/W Junction to Case 12
Junction to Base θJb 5.4 °C/W Junction to Base 12
Junction to Air, still air θJA0 50 °C/W Junction to Air, still air 12
Junction to Air, 5 m/s air flow θJA5 38 °C/W Junction to Air, 5 m/s air flow 12

CAD (KiCad official)

  • Symbol: 9FGV0241AKILF
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: 9fgv0241akilf-etched.step / 9fgv0241akilf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 9fgv0241akilf.step / 9fgv0241akilf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (17 pp, sha256 a8d17bb591289429, retrieved 2026-11-02, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF