component
9DBL411BGILF
Public Made by Adomby adom
RENESAS Clock Buffers, Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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9DBL411BGILF
RENESAS · Clock Buffers, Drivers · TSSOP-20
9DBL411BGILF from RENESAS, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE0# | input | Output enable for the DIF0 output: 0 = enabled, 1 = Low-Low. |
| 2 | DIF_INC | input | Complement side of the differential input clock. |
| 3 | DIF_INT | input | True side of the differential input clock. |
| 4 | VDDA | power_in | 3.3V power for the analog core, with a supply voltage of 3.000 V to 3.600 V. |
| 5 | GNDA | power_in | Ground for the analog core. |
| 6 | OE3# | input | Output enable for the DIF3 output: 0 = enabled, 1 = Low-Low. |
| 7 | DIF3C_LPR | output | Complement clock of the low power differential clock pair; no 50 ohm shunt resistor to GND is needed. |
| 8 | DIF3T_LPR | output | True clock of the low power differential clock pair; no 50 ohm shunt resistor to GND is needed. |
| 9 | VDD_IO | power_in | Power supply for the low power differential outputs, nominal 1.05 V to 3.3 V. |
| 10 | GND | power_in | Ground pin. |
| 11 | DIF2C_LPR | output | Complement clock of the low power differential clock pair; no 50 ohm shunt resistor to GND is needed. |
| 12 | DIF2T_LPR | output | True clock of the low power differential clock pair; no 50 ohm shunt resistor to GND is needed. |
| 13 | OE2# | input | Output enable for the DIF2 output: 0 = enabled, 1 = Low-Low. |
| 14 | DIF1C_LPR | output | Complement clock of the low power differential clock pair; no 50 ohm shunt resistor to GND is needed. |
| 15 | DIF1T_LPR | output | True clock of the low power differential clock pair; no 50 ohm shunt resistor to GND is needed. |
| 16 | OE1# | input | Output enable for the DIF1 output: 0 = enabled, 1 = Low-Low. |
| 17 | GND | power_in | Ground pin. |
| 18 | VDD_IO | power_in | Power supply for the low power differential outputs, nominal 1.05 V to 3.3 V. |
| 19 | DIF0C_LPR | output | Complement clock of the low power differential clock pair; no 50 ohm shunt resistor to GND is needed. |
| 20 | DIF0T_LPR | output | True clock of the low power differential clock pair; no 50 ohm shunt resistor to GND is needed. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | TSSOP-20 |
| Category | Clock and Timing |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum Supply Voltage (Core Supply Voltage) | VDDA | 4.6 | V | Core Supply Voltage | 5 | ||
| Maximum Supply Voltage (Low-Voltage Differential I/O) | VDD_IO | 0.99 | 3.8 | V | Low-Voltage Differential I/O | 5 | |
| Maximum Input Voltage | VIH | 4.6 | V | 3.3V LVCMOS Inputs | 5 | ||
| Ambient Operating Temperature (Industrial Range) | TambIND | -40 | 85 | °C | Industrial Range | 5 | |
| Storage Temperature | Ts | -65 | 150 | °C | 5 | ||
| Input ESD protection (Human Body Model) | ESD prot | 2000 | V | Human Body Model | 5 | ||
| Supply Voltage (VDDA) | VDDA | 3 | 3.6 | V | 5 | ||
| Supply Voltage (Low-Voltage Differential I/O Supply) | VDDxxx_IO | 0.99 | 3.6 | V | Low-Voltage Differential I/O Supply | 5 | |
| Input Low Voltage | VILSE | 0.8 | V | Single-ended inputs | 5 | ||
| Differential Input High Voltage | VIHDIF | 600 | 1150 | mV | Differential inputs (single-ended measurement) | 5 | |
| Differential Input Low Voltage | VILDIF | 300 | mV | Differential inputs (single-ended measurement) | 5 | ||
| Input Slew Rate | dv/dt | 0.4 | 8 | V/ns | Measured differentially | 5 | |
| Input Leakage Current | IIN | -5 | 5 | uA | VIN = VDD, VIN = GND | 5 | |
| VDDA supply current | IDD_3.3V | 20 | mA | 5 | |||
| VDD_IO supply current | IDD_IO_133M | 20 | mA | VDD_IO supply @ fOP = 133MHz | 5 | ||
| VDDA supply current, input stopped, OE# pins all high | IDD_SB_3.3V | 750 | uA | Input stopped, OE# pins all high | 5 | ||
| VDD_IO supply, input stopped, OE# pins all high | IDD_SBIO | 150 | uA | Input stopped, OE# pins all high | 5 | ||
| Input Frequency | Fi | 15 | 150 | MHz | VDD = 3.3 V | 5 | |
| Pin Inductance | Lpin | 7 | nH | 5 | |||
| Input Capacitance (logic inputs) | CIN | 1.5 | 5 | pF | Logic Inputs | 5 | |
| Output pin capacitance | COUT | 6 | pF | Output pin capacitance | 5 | ||
| OE# latency | TOE#LAT | 1 | 3 | periods | At least one OE# is low; number of clocks to enable or disable output from assertion/deassertion of OE# | 5 | |
| Clock stabilization time (from all OE# high to first OE# low) | TSTAB | 150 | ns | Delay from assertion of first OE# to first clock out (input clock running, device in power down state) | 5 | ||
| Output enable after OE# de-assertion | Tdrive_OE# | 10 | ns | 5 | |||
| Fall time of OE# inputs | TFALL | 5 | ns | 5 | |||
| Rise time of OE# inputs | TRISE | 5 | ns | 5 | |||
| Rising Edge Slew Rate | tSLR | 1.5 | 4 | V/ns | Differential Measurement | 6 | |
| Falling Edge Slew Rate | tFLR | 1.5 | 4 | V/ns | Differential Measurement | 6 | |
| Slew Rate Variation | tSLVAR | 20 | % | Single-ended Measurement | 6 | ||
| Maximum Output Voltage | VHIGH | 1150 | mV | Includes overshoot | 6 | ||
| Minimum Output Voltage | VLOW | -300 | mV | Includes undershoot | 6 | ||
| Differential Voltage Swing | VSWING | 1200 | mV | Differential Measurement | 6 | ||
| Crossing Point Voltage | VXABS | 300 | 550 | mV | Single-ended Measurement | 6 | |
| Crossing Point Variation | VXABSVAR | 140 | mV | Single-ended Measurement | 6 | ||
| Duty Cycle Distortion | DCYCDIS0 | 3 | % | Differential Measurement, fIN<=133.33MHz | 6 | ||
| Additive Cycle to Cycle Jitter | DIFJC2CADD | 15 | ps | Differential Measurement, Additive | 6 | ||
| DIF[3:0] Skew | DIFSKEW | 50 | ps | Differential Measurement | 6 | ||
| Propagation Delay | tPD | 2.5 | 3.5 | ns | Input to output Delay | 6 | |
| Additive Phase Jitter - PCIe Gen1 | tphase_add PCIG1 | 6 | ps Pk-Pk | 1.5MHz < 22MHz | 6 | ||
| Additive Phase Jitter - PCIe Gen2 High Band | tphase_add PCIG2HI | 0.16 | ps rms | High Band is 1.5MHz to Nyquist (50MHz) | 6 | ||
| Additive Phase Jitter - PCIe Gen2 Low Band | tphase_add PCIG2LO | 0.07 | ps rms | Low Band is 10KHz to 1.5MHz | 6 | ||
| Additive Phase Jitter - PCIe Gen3 | tphase_add PCIG2LO | 0.2 | ps rms | 2M-4M, 2M-5M filter | 6 | ||
| Additive Phase Jitter - QPI133 (6.4GBs, 12 UI) | tphase_add QPI6G4 | 0.04 | ps rms | 11MHz to 33MHz | 6 |
CAD (KiCad official)
- Symbol:
9DBL411BGILF - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
9dbl411bgilf-etched.step/9dbl411bgilf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);9dbl411bgilf.step/9dbl411bgilf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (10 pp, sha256
70fa6701e0fc6ed5, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).