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97A8

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WEIDA Thyristors (SCR)/Modules, SOT-23-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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97A8

WEIDA · Thyristors (SCR)/Modules · SOT-23-3L

97A8 from WEIDA, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 T1 passive Main terminal T1 of the triac (symbol T1(1)); the gate trigger specs (IGT 5 mA max quadrants I-II-III, 10 mA quadrant IV at VD=12V, RL=33Ω) are measured against this terminal.
2 T2 passive Main terminal T2 of the triac (symbol T2(2)), rated for VDRM/VRRM 600/800 V and IT(RMS) 0.8 A.
3 G input Gate trigger input (symbol G(3)) with VGT max 1.3 V and peak gate current IGM of 1 A.

Key specifications

Parameter Value
Manufacturer WEIDA
Package SOT-23-3L
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage junction temperature range Tstg -40 150 ℃ 1
Operating junction temperature range Tj -40 125 ℃ 1
Repetitive peak off-state voltage VDRM 600 800 V Tj=25℃; printed as 600/800 for the series; 97A8 voltage class not confirmed 1
Repetitive peak reverse voltage VRRM 600 800 V Tj=25℃; printed as 600/800 for the series; 97A8 voltage class not confirmed 1
RMS on-state current IT(RMS) 0.8 A 1
Non repetitive surge peak on-state current ITSM 9 A full cycle, F=50Hz 1
I2t value for fusing I2t 0.45 A2s tp=10ms 1
Critical rate of rise of on-state current, Ⅰ-Ⅱ-Ⅲ dI/dt 50 A/μs IG=2×IGT; Ⅰ-Ⅱ-Ⅲ quadrants 1
Critical rate of rise of on-state current, Ⅳ dI/dt 10 A/μs IG=2×IGT; Ⅳ quadrant 1
Peak gate current IGM 1 A 1
Average gate power dissipation PG(AV) 0.1 W 1
Peak gate power PGM 5 W 1
Gate trigger current, Ⅰ-Ⅱ-Ⅲ IGT 5 mA VD=12V, RL=33Ω; Ⅰ-Ⅱ-Ⅲ quadrants 2
Gate trigger current, Ⅳ IGT 10 mA VD=12V, RL=33Ω; Ⅳ quadrant 2
Gate trigger voltage VGT 1.3 V Ⅰ-Ⅱ-Ⅲ-Ⅳ quadrants 2
Gate non-trigger voltage VGD 0.2 V VD=VDRM, Tj=125℃, RL=3.3kΩ; Ⅰ-Ⅱ-Ⅲ-Ⅳ quadrants 2
Holding current IH 7 mA IT=100mA 2
Latching current, Ⅰ-Ⅲ-Ⅳ IL 5 mA IG=1.2IGT; Ⅰ-Ⅲ-Ⅳ quadrants 2
Latching current, Ⅱ IL 20 mA IG=1.2IGT; Ⅱ quadrant 2
Critical rate of rise of off-state voltage dV/dt 50 V/µs VD=0.66×VDRM, Tj=125℃, gate open 2
On-state voltage VTM 1.5 V ITM=1.1A, tp=380μs, Tj=25℃ 2
Repetitive peak off-state current IDRM/IRRM 5 µA VDRM=VRRM, Tj=25℃ 2
Repetitive peak off-state current IDRM/IRRM 0.5 mA VDRM=VRRM, Tj=125℃ 2
Thermal resistance junction to case (AC), SOT-223/SOT-23-2L Rth(j-c) 45 ℃/W junction to case (AC); SOT-223/SOT-23-2L as printed 2

CAD (KiCad official)

  • Symbol: 97A8
  • Footprint: Package_TO_SOT_SMD:SOT-23-3
  • 3D model: SOT-23-3L (KiCad packages3D, STEP)
  • 3D model files: 97a8-etched.step / 97a8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 97a8.step / 97a8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WEIDA datasheet (6 pp, sha256 d5c165704719d1a3, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF