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93LC86C-I

Microchip Tech · EEPROM · SOIC-8

93LC86C-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CS	input	Chip Select: a high level selects the device, a low level deselects it and forces Standby mode, and CS must be low for 250 ns minimum (TCSL) between consecutive instructions.
2	CLK	input	Serial Clock synchronizes communication with the master; opcodes, address and data bits are clocked in (and data out) on the positive edge of CLK.
3	DI	input	Data In is used to clock in a Start bit, opcode, address and data synchronously with the CLK input.
4	DO	output	Data Out outputs data synchronously with CLK in Read mode and provides READY/BUSY status during ERASE and WRITE cycles; it is HIGH-Z when not outputting.
5	VSS	power_in	Ground.
6	ORG	input	Organization select: tied to VCC or logic high selects x16 organization, tied to VSS or logic low selects x8, and it must be tied to a valid logic level.
7	PE	input	Program Enable: tied to VCC allows programming, tied to VSS inhibits programming, and the pin cannot be floated.
8	VCC	power_in	Power supply, 2.5V to 5.5V for the 93LC86C, with absolute maximum of 7.0V.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	SOIC-8
Category	Memory
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC			7	V		2
Input/output voltage w.r.t. VSS		-0.6			V	-0.6V to VCC +1.0V	2
Storage temperature		-65		150	°C		2
Ambient temperature with power applied		-40		125	°C		2
ESD protection on all pins		4			kV	≥ 4 kV	2
Supply voltage range 93LC86C	VCC	2.5		5.5	V		1
Industrial operating temperature	TA	-40		85	°C	Industrial (I)	2
High-level input voltage	VIH1	2			V	VCC ≥ 2.7V	2
Low-level input voltage	VIL1	-0.3		0.8	V	VCC ≥ 2.7V	2
Low-level input voltage	VIL2	-0.3			V	VCC < 2.7V	2
Low-level output voltage	VOL1			0.4	V	IOL = 2.1 mA, VCC = 4.5V	2
Low-level output voltage	VOL2			0.2	V	IOL = 100 µA, VCC = 2.5V	2
High-level output voltage	VOH1	2.4			V	IOH = -400 µA, VCC = 4.5V	2
Input leakage current	ILI	-1		1	µA	VIN = VSS to VCC	2
Output leakage current	ILO	-1		1	µA	VOUT = VSS to VCC	2
Pin capacitance (all inputs/outputs)	CIN, COUT			7	pF	VIN/VOUT = 0V (Note 1), TA = 25°C, FCLK = 1 MHz	2
Standby current	ICCS			1	µA	I, Temp, CLK = CS = 0V, ORG = DI = VSS or VCC	2
VCC voltage detect	VPOR		1.5		V	93AA86A/B/C, 93LC86A/B/C (Note 1)	2
Clock frequency	FCLK			3	MHz	4.5V ≤ VCC < 5.5V	3
Clock frequency	FCLK			2	MHz	2.5V ≤ VCC < 4.5V	3
Clock high time	TCKH	200			ns	4.5V ≤ VCC < 5.5V	3
Clock high time	TCKH	250			ns	2.5V ≤ VCC < 4.5V	3
Clock low time	TCKL	100			ns	4.5V ≤ VCC < 5.5V	3
Clock low time	TCKL	200			ns	2.5V ≤ VCC < 4.5V	3
Chip Select setup time	TCSS	50			ns	4.5V ≤ VCC < 5.5V	3
Chip Select setup time	TCSS	100			ns	2.5V ≤ VCC < 4.5V	3
Chip Select hold time	TCSH	0			ns	1.8V ≤ VCC < 5.5V	3
Chip Select low time	TCSL	250			ns	1.8V ≤ VCC < 5.5V	3
Data input setup time	TDIS	50			ns	4.5V ≤ VCC < 5.5V	3
Data input setup time	TDIS	100			ns	2.5V ≤ VCC < 4.5V	3
Data input hold time	TDIH	50			ns	4.5V ≤ VCC < 5.5V	3
Data input hold time	TDIH	100			ns	2.5V ≤ VCC < 4.5V	3
Data output delay time	TPD			100	ns	4.5V ≤ VCC < 5.5V, CL = 100 pF	3
Data output delay time	TPD			250	ns	2.5V ≤ VCC < 4.5V, CL = 100 pF	3
Data output disable time	TCZ			100	ns	4.5V ≤ VCC < 5.5V, (Note 1)	3
Data output disable time	TCZ			200	ns	1.8V ≤ VCC < 4.5V, (Note 1)	3
Status valid time	TSV			200	ns	4.5V ≤ VCC < 5.5V, CL = 100 pF	3
Status valid time	TSV			300	ns	2.5V ≤ VCC < 4.5V, CL = 100 pF	3
Program cycle time	TWC			5	ms	ERASE/WRITE mode (AA and LC versions)	3
ERAL cycle time	TEC			6	ms	ERAL mode, 4.5V ≤ VCC ≤ 5.5V	3
WRAL cycle time	TWL			15	ms	WRAL mode, 4.5V ≤ VCC ≤ 5.5V	3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts		tin	packaging including 8-lead MSOP, 6-lead SOT-23, and 8-lead TSSOP. Pb-free (Pure Matte Sn) finish is	1

CAD (KiCad official)

Symbol: 93LC86C-I
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: 93lc86c-i-etched.step / 93lc86c-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 93lc86c-i.step / 93lc86c-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (26 pp, sha256 03c52af7622ff46d, retrieved 2026-10-23, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF