component
93LC86-I
Public Made by Adomby adom
Microchip Tech EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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93LC86-I
Microchip Tech · EEPROM · SOIC-8
93LC86-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select: a high level selects the device and a low level deselects it into Standby mode, and CS must be low for at least 250 ns (TCSL) between consecutive instructions. |
| 2 | CLK | input | Serial Clock that synchronizes communication, clocking opcode, address and data bits in and data bits out on the positive edge, and is a don't-care when CS is low. |
| 3 | DI | input | Serial Data Input used to clock in the Start bit, opcode, address and data synchronously with CLK. |
| 4 | DO | tri_state | Serial Data Output that outputs read data synchronously with CLK and gives Ready/Busy status during erase/write while CS is high, and is high-Z otherwise. |
| 5 | VSS | power_in | Ground. |
| 6 | ORG | input | Memory organization select: tied to VCC selects x16, tied to VSS selects x8, and an internal pull-up selects x16 when left unconnected. |
| 7 | PE | input | Program Enable: floated or tied to VCC allows programming, tied to VSS inhibits programming, and an internal pull-up enables programming when left floating. |
| 8 | VCC | power_in | Power supply, +2.5V to +6.0V operating range (7.0V absolute maximum). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage | VIH1 | 2 | V | VCC ≥ 2.7V (max VCC + 1) | 3 | ||
| High-level input voltage | VIH2 | 0.7 | V | VCC < 2.7V; min 0.7 VCC (unit: x VCC), max VCC + 1 | 3 | ||
| Low-level input voltage | VIL1 | -0.3 | 0.8 | V | VCC ≥ 2.7V | 3 | |
| Low-level output voltage | VOL1 | 0.4 | V | IOL = 2.1 mA; VCC = 4.5V | 3 | ||
| Low-level output voltage | VOL2 | 0.2 | V | IOL =100 µA; VCC = VCC Min. | 3 | ||
| High-level output voltage | VOH1 | 2.4 | V | IOH = -400 µA; VCC = 4.5V | 3 | ||
| Input leakage current | ILI | -10 | 10 | µA | VIN = 0.1V to VCC | 3 | |
| Output leakage current | ILO | -10 | 10 | µA | VOUT = 0.1V to VCC | 3 | |
| Pin capacitance (all inputs/outputs) | CINT | 7 | pF | TA = +25°C, FCLK = 1 MHz (Note 1) | 3 | ||
| Operating current write | ICC write | 3 | mA | VCC = 5.5V | 3 | ||
| Operating current read | ICC read | 1 | mA | FCLK = 3 MHz; VCC = 5.5V | 3 | ||
| Operating current read | ICC read | 500 | µA | FCLK = 1 MHz; VCC = 3.0V | 3 | ||
| Standby current | ICCS | 100 | µA | CLK = CS = 0V; VCC = 5.5V; DI = PE = VSS; ORG = VSS or VCC | 3 | ||
| Standby current | ICCS | 30 | µA | CLK = CS = 0V; VCC = 3.0V; DI = PE = VSS; ORG = VSS or VCC | 3 | ||
| Clock frequency | FCLK | 3 | MHz | 4.5V ≤ VCC ≤ 6.0V | 4 | ||
| Clock frequency | FCLK | 2 | MHz | 2.5V ≤ VCC < 4.5V | 4 | ||
| Clock high time | TCKH | 200 | ns | 4.5V ≤ VCC ≤ 6.0V | 4 | ||
| Clock high time | TCKH | 300 | ns | 2.5V ≤ VCC < 4.5V | 4 | ||
| Clock low time | TCKL | 100 | ns | 4.5V ≥ VCC ≤ 6.0V | 4 | ||
| Clock low time | TCKL | 200 | ns | 2.5V ≤ VCC < 4.5V | 4 | ||
| Chip select setup time | TCSS | 50 | ns | 4.5V ≤ VCC ≤ 6.0V, Relative to CLK | 4 | ||
| Chip select setup time | TCSS | 100 | ns | 2.5V ≤ VCC < 4.5V, Relative to CLK | 4 | ||
| Chip select hold time | TCSH | 0 | ns | 4 | |||
| Chip select low time | TCSL | 250 | ns | Relative to CLK | 4 | ||
| Data input setup time | TDIS | 50 | ns | 4.5V ≤ VCC ≤ 6.0V, Relative to CLK | 4 | ||
| Data input setup time | TDIS | 100 | ns | 2.5V ≤ VCC <4.5V, Relative to CLK | 4 | ||
| Data input hold time | TDIH | 50 | ns | 4.5V ≤ VCC ≤ 6.0V, Relative to CLK | 4 | ||
| Data input hold time | TDIH | 100 | ns | 2.5V ≤ VCC < 4.5V, Relative to CLK | 4 | ||
| Data output delay time | TPD | 100 | ns | 4.5V ≤ VCC ≤ 6.0V, CL = 100 pF | 4 | ||
| Data output delay time | TPD | 250 | ns | 2.5V ≤ VCC < 4.5V, CL = 100 pF | 4 | ||
| Data output disable time | TCZ | 100 | ns | 4.5V ≤ VCC ≤ 6.0V | 4 | ||
| Data output disable time | TCZ | 500 | ns | 2.5V ≤ VCC < 4.5V (Note 1) | 4 | ||
| Status valid time | Tsv | 200 | ns | 4.5V ≥ VCC ≤ 6.0V, CL = 100 pF | 4 | ||
| Status valid time | Tsv | 300 | ns | 2.5V ≤ VCC <4.5V, CL = 100 pF | 4 | ||
| Program cycle time | TWC | 5 | ms | Erase/Write mode | 4 | ||
| Program cycle time | TEC | 15 | ms | ERAL mode | 4 | ||
| Program cycle time | TWL | 30 | ms | WRAL mode | 4 | ||
| Supply voltage | VCC | 7 | V | 2 | |||
| All inputs and outputs w.r.t. VSS | -0.6 | V | max is Vcc + 1.0V | 2 | |||
| Storage temperature | -65 | 150 | °C | 2 | |||
| Ambient temperature with power applied | -40 | 125 | °C | 2 | |||
| Soldering temperature of leads | 300 | °C | 10 seconds | 2 | |||
| ESD protection on all pins | 4 | kV | 2 | ||||
| Supply voltage range | VCC | 2.5 | 6 | V | 3 | ||
| Industrial operating temperature | TA | -40 | 85 | °C | Industrial (I) | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | 8-Lead Plastic Small Outline (SN), Narrow, 150 mil Body (SOIC) Foot Angle φ 048048 | 14 |
CAD (KiCad official)
- Symbol:
93LC86-I - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
93lc86-i-etched.step/93lc86-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);93lc86-i.step/93lc86-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (22 pp, sha256
d7dd49d5ffbd1a0c, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 93LC86-I
**Microchip Tech** · EEPROM · SOIC-8
93LC86-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip Select: a high level selects the device and a low level deselects it into Standby mode, and CS must be low for at least 250 ns (TCSL) between consecutive instructions. |
| 2 | CLK | input | Serial Clock that synchronizes communication, clocking opcode, address and data bits in and data bits out on the positive edge, and is a don't-care when CS is low. |
| 3 | DI | input | Serial Data Input used to clock in the Start bit, opcode, address and data synchronously with CLK. |
| 4 | DO | tri_state | Serial Data Output that outputs read data synchronously with CLK and gives Ready/Busy status during erase/write while CS is high, and is high-Z otherwise. |
| 5 | VSS | power_in | Ground. |
| 6 | ORG | input | Memory organization select: tied to VCC selects x16, tied to VSS selects x8, and an internal pull-up selects x16 when left unconnected. |
| 7 | PE | input | Program Enable: floated or tied to VCC allows programming, tied to VSS inhibits programming, and an internal pull-up enables programming when left floating. |
| 8 | VCC | power_in | Power supply, +2.5V to +6.0V operating range (7.0V absolute maximum). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage | VIH1 | 2 | | | V | VCC ≥ 2.7V (max VCC + 1) | 3 |
| High-level input voltage | VIH2 | 0.7 | | | V | VCC < 2.7V; min 0.7 VCC (unit: x VCC), max VCC + 1 | 3 |
| Low-level input voltage | VIL1 | -0.3 | | 0.8 | V | VCC ≥ 2.7V | 3 |
| Low-level output voltage | VOL1 | | | 0.4 | V | IOL = 2.1 mA; VCC = 4.5V | 3 |
| Low-level output voltage | VOL2 | | | 0.2 | V | IOL =100 µA; VCC = VCC Min. | 3 |
| High-level output voltage | VOH1 | 2.4 | | | V | IOH = -400 µA; VCC = 4.5V | 3 |
| Input leakage current | ILI | -10 | | 10 | µA | VIN = 0.1V to VCC | 3 |
| Output leakage current | ILO | -10 | | 10 | µA | VOUT = 0.1V to VCC | 3 |
| Pin capacitance (all inputs/outputs) | CINT | | | 7 | pF | TA = +25°C, FCLK = 1 MHz (Note 1) | 3 |
| Operating current write | ICC write | | | 3 | mA | VCC = 5.5V | 3 |
| Operating current read | ICC read | | | 1 | mA | FCLK = 3 MHz; VCC = 5.5V | 3 |
| Operating current read | ICC read | | | 500 | µA | FCLK = 1 MHz; VCC = 3.0V | 3 |
| Standby current | ICCS | | | 100 | µA | CLK = CS = 0V; VCC = 5.5V; DI = PE = VSS; ORG = VSS or VCC | 3 |
| Standby current | ICCS | | | 30 | µA | CLK = CS = 0V; VCC = 3.0V; DI = PE = VSS; ORG = VSS or VCC | 3 |
| Clock frequency | FCLK | | | 3 | MHz | 4.5V ≤ VCC ≤ 6.0V | 4 |
| Clock frequency | FCLK | | | 2 | MHz | 2.5V ≤ VCC < 4.5V | 4 |
| Clock high time | TCKH | 200 | | | ns | 4.5V ≤ VCC ≤ 6.0V | 4 |
| Clock high time | TCKH | 300 | | | ns | 2.5V ≤ VCC < 4.5V | 4 |
| Clock low time | TCKL | 100 | | | ns | 4.5V ≥ VCC ≤ 6.0V | 4 |
| Clock low time | TCKL | 200 | | | ns | 2.5V ≤ VCC < 4.5V | 4 |
| Chip select setup time | TCSS | 50 | | | ns | 4.5V ≤ VCC ≤ 6.0V, Relative to CLK | 4 |
| Chip select setup time | TCSS | 100 | | | ns | 2.5V ≤ VCC < 4.5V, Relative to CLK | 4 |
| Chip select hold time | TCSH | 0 | | | ns | | 4 |
| Chip select low time | TCSL | 250 | | | ns | Relative to CLK | 4 |
| Data input setup time | TDIS | 50 | | | ns | 4.5V ≤ VCC ≤ 6.0V, Relative to CLK | 4 |
| Data input setup time | TDIS | 100 | | | ns | 2.5V ≤ VCC <4.5V, Relative to CLK | 4 |
| Data input hold time | TDIH | 50 | | | ns | 4.5V ≤ VCC ≤ 6.0V, Relative to CLK | 4 |
| Data input hold time | TDIH | 100 | | | ns | 2.5V ≤ VCC < 4.5V, Relative to CLK | 4 |
| Data output delay time | TPD | | | 100 | ns | 4.5V ≤ VCC ≤ 6.0V, CL = 100 pF | 4 |
| Data output delay time | TPD | | | 250 | ns | 2.5V ≤ VCC < 4.5V, CL = 100 pF | 4 |
| Data output disable time | TCZ | | | 100 | ns | 4.5V ≤ VCC ≤ 6.0V | 4 |
| Data output disable time | TCZ | | | 500 | ns | 2.5V ≤ VCC < 4.5V (Note 1) | 4 |
| Status valid time | Tsv | | | 200 | ns | 4.5V ≥ VCC ≤ 6.0V, CL = 100 pF | 4 |
| Status valid time | Tsv | | | 300 | ns | 2.5V ≤ VCC <4.5V, CL = 100 pF | 4 |
| Program cycle time | TWC | | | 5 | ms | Erase/Write mode | 4 |
| Program cycle time | TEC | | | 15 | ms | ERAL mode | 4 |
| Program cycle time | TWL | | | 30 | ms | WRAL mode | 4 |
| Supply voltage | VCC | | | 7 | V | | 2 |
| All inputs and outputs w.r.t. VSS | | -0.6 | | | V | max is Vcc + 1.0V | 2 |
| Storage temperature | | -65 | | 150 | °C | | 2 |
| Ambient temperature with power applied | | -40 | | 125 | °C | | 2 |
| Soldering temperature of leads | | | | 300 | °C | 10 seconds | 2 |
| ESD protection on all pins | | | | 4 | kV | | 2 |
| Supply voltage range | VCC | 2.5 | | 6 | V | | 3 |
| Industrial operating temperature | TA | -40 | | 85 | °C | Industrial (I) | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | 8-Lead Plastic Small Outline (SN), Narrow, 150 mil Body (SOIC) Foot Angle φ 048048 | 14 |
## CAD (KiCad official)
- Symbol: `93LC86-I`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `93lc86-i-etched.step` / `93lc86-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `93lc86-i.step` / `93lc86-i.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/93lc86-i-datasheet.pdf) (22 pp, sha256 `d7dd49d5ffbd1a0c`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/93lc86-i-datasheet.pdf)