component

93LC56BXT-I

Public Made by Adom

by adom

Microchip Tech Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface ics93lc56bxt-ifactory-2.0.0extractor-text

Verified 93LC56BXT-I

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 93LC56BXT-I · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 36-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1v4qykly/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 93lc56bxt-i.kicad_sym✓ 93lc56bxt-i.kicad_mod✓ 93lc56bxt-i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers 93lc56bxt-i: viewers · Ray 3d ago
93lc56bxt-i-etched.glb Publish 0.1.0 · Ray 3d ago
93lc56bxt-i-etched.step 93lc56bxt-i: factory component page (tier=mfr) · Ray 3d ago
93lc56bxt-i-hero.glb 93lc56bxt-i: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
93lc56bxt-i-hero.overlay.json Publish 0.1.0 · Ray 3d ago
93lc56bxt-i.glb Publish 0.1.0 · Ray 3d ago
93lc56bxt-i.kicad_mod Publish 0.1.0 · Ray 3d ago
93lc56bxt-i.kicad_sym Publish 0.1.0 · Ray 3d ago
93lc56bxt-i.lbr Publish 0.1.0 · Ray 3d ago
93lc56bxt-i.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 3d ago

93LC56BXT-I

Microchip Tech · Pre-ordered Chips · SOIC-8

93LC56BXT-I from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection on this device; the pin is not connected internally.
2 VCC power_in Power supply pin; the 93LC56 family operates from 2.5 V to 5.5 V.
3 CS input Chip Select: a high level selects the device and a low level deselects it and forces Standby mode, and CS must be low for 250 ns minimum (TCSL) between consecutive instructions.
4 CLK input Serial Clock: opcodes, address and data bits are clocked in on the positive edge of CLK, and data bits are clocked out on the positive edge of CLK.
5 DI input Data In: clocks in the Start bit, opcode, address and data synchronously with the CLK input.
6 DO output Data Out: outputs read data synchronously with CLK (TPD after the positive edge of CLK) and indicates Ready/Busy status during erase and write cycles when CS is brought high after being low for TCSL.
7 VSS power_in Ground reference for the device.
8 NC unconnected No internal connection on the 93XX56A/B devices (ORG is used only on the 93XX56C, where it selects x8 or x16 organization).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 7 V 3
All inputs and outputs w.r.t. VSS -0.6 V W.r.t. VSS; upper limit VCC +1.0 V 3
Storage temperature -65 150 °C 3
Ambient temperature with power applied -40 125 °C 3
Supply voltage VCC 2.5 5.5 V 93LC56B (Device Selection Table, VCC range) 1
Ambient temperature, industrial TA -40 85 °C Industrial (I) grade 3
High-level input voltage VIH1 2 V VCC ≥ 2.7V 3
Low-level input voltage VIL1 -0.3 0.8 V VCC ≥ 2.7V 3
Low-level input voltage VIL2 -0.3 V VCC < 2.7V 3
Low-level output voltage Vol1 0.4 V IOL = 2.1 mA, VCC = 4.5V 3
Low-level output voltage Vol2 0.2 V IOL = 100 µA, VCC = 2.5V 3
High-level output voltage VOH1 2.4 V IOH = -400 µA, VCC = 4.5V 3
Input leakage current ILI -1 1 µA VIN = VSS or VCC 3
Output leakage current ILO -1 1 µA VOUT = VSS or VCC 3
Pin capacitance (all inputs/outputs) CIN, COUT 7 pF VIN/VOUT = 0V (Note 1); TA = 25°C, FCLK = 1 MHz 3
Write current ICC write 500 mA FCLK = 3 MHz, VCC = 5.5V 3
Write current ICC write 2 µA FCLK = 2 MHz, VCC = 2.5V 3
Standby current ICCS 1 µA I, Temp; CLK = CS = 0V; ORG = DI = VSS or VCC (Note 2) (Note 3) 3
Clock frequency FCLK 2 MHz 2.5V ≤ VCC < 5.5V 4
Clock high time TCKH 250 ns 2.5V ≤ VCC < 5.5V 4
Clock low time TCKL 200 ns 2.5V ≤ VCC < 5.5V 4
Chip Select setup time TCSS 50 ns 4.5V ≤ VCC < 5.5V 4
Chip Select setup time TCSS 100 ns 2.5V ≤ VCC < 4.5V 4
Chip Select hold time TCSH 0 ns 1.8V ≤ VCC < 5.5V 4
Chip Select low time TCSL 250 ns 1.8V ≤ VCC < 5.5V 4
Data input setup time TDIS 100 ns 2.5V ≤ VCC < 5.5V 4
Data input hold time TDIH 100 ns 2.5V ≤ VCC < 5.5V 4
Data output delay time TPD 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 4
Data output delay time TPD 250 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF 4
Data output disable time TCZ 100 ns 4.5V ≤ VCC < 5.5V (Note 1) 4
Data output disable time TCZ 200 ns 1.8V ≤ VCC < 4.5V (Note 1) 4
Status valid time TSV 200 ns 4.5V ≤ VCC < 5.5V, CL = 100 pF 4
Status valid time TSV 300 ns 2.5V ≤ VCC < 4.5V, CL = 100 pF 4
Program cycle time TWC 6 ms Erase/Write mode (AA and LC versions) 4
ERAL mode time TEC 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V 4
WRAL mode time TWL 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V 4
VCC voltage detect VPOR 1.5 V 93AA56A/B/C, 93LC56A/B/C (Note 1) 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin SOT-23, 8-lead 2x3 DFN/TDFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish. 1

CAD (KiCad official)

  • Symbol: 93LC56BXT-I
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: 93lc56bxt-i-etched.step / 93lc56bxt-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 93lc56bxt-i.step / 93lc56bxt-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (36 pp, sha256 db7e9d89e8e34db6, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF