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93LC56B-I

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Microchip Tech EEPROM, PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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93LC56B-I

Microchip Tech · EEPROM · PDIP-8

93LC56B-I from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select: a high level selects the device and a low level deselects it into Standby mode, and CS must be low for 250 ns minimum (TCSL) between consecutive instructions.
2 CLK input Serial Clock synchronizes communication, with opcodes, address and data clocked in and data clocked out on its positive edge, and it is a don't-care while CS is low.
3 DI input Serial Data Input clocks in the Start bit, opcode, address and data synchronously with CLK.
4 DO output Serial Data Output drives read data synchronously with CLK (TPD after the positive edge) and also shows Ready/Busy status during erase/write when CS is brought high after TCSL.
5 VSS power_in Ground reference for the device.
6 ORG/NC unconnected On the 93LC56B this pin is No Internal Connection, since the ORG function applies only to the 93XX56C word-size select.
7 NC unconnected No internal connection.
8 VCC power_in Power supply; the 93LC56B operates from 2.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package PDIP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level input voltage VIH1 2 V VCC >= 2.7V 3
Low-level input voltage VIL1 -0.3 0.8 V VCC >= 2.7V 3
Low-level input voltage VIL2 -0.3 V VCC < 2.7V 3
Low-level output voltage VOL1 0.4 V IOL = 2.1 mA, VCC = 4.5V 3
Low-level output voltage VOL2 0.2 V IOL = 100 µA, VCC = 2.5V 3
High-level output voltage VOH1 2.4 V IOH = -400 µA, VCC = 4.5V 3
Input leakage current ILI -1 1 µA VIN = VSS or VCC 3
Output leakage current ILO -1 1 µA VOUT = VSS or VCC 3
Pin capacitance (all inputs/outputs) CIN, COUT 7 pF VIN/VOUT = 0V (Note 1); TA = 25°C, FCLK = 1 MHz 3
Write current ICC write 500 mA FCLK = 3 MHz, Vcc = 5.5V 3
Write current ICC write 2 µA FCLK = 2 MHz, Vcc = 2.5V 3
Read current ICC read 100 mA FCLK = 3 MHz, VCC = 5.5V 3
Read current ICC read 1 µA FCLK = 2 MHz, VCC = 3.0V 3
Read current ICC read 500 µA FCLK = 2 MHz, VCC = 2.5V 3
Standby current ICCS 1 µA I - Temp; CLK = CS = 0V; ORG = DI = VSS or VCC 3
Clock frequency FCLK 2 MHz 2.5V <= VCC < 5.5V 4
Clock high time TCKH 250 ns 2.5V <= VCC < 5.5V 4
Clock low time TCKL 200 ns 2.5V <= VCC < 5.5V 4
Chip Select setup time TCSS 50 ns 4.5V <= VCC < 5.5V 4
Chip Select setup time TCSS 100 ns 2.5V <= VCC < 4.5V 4
Chip Select hold time TCSH 0 ns 1.8V <= VCC < 5.5V 4
Chip Select low time TCSL 250 ns 1.8V <= VCC < 5.5V 4
Data input setup time TDIS 100 ns 2.5V <= VCC < 5.5V 4
Data input hold time TDIH 100 ns 2.5V <= VCC < 5.5V 4
Data output delay time TPD 200 ns 4.5V <= VCC < 5.5V, CL = 100 pF 4
Data output delay time TPD 250 ns 2.5V <= VCC < 4.5V, CL = 100 pF 4
Data output disable time TCZ 100 ns 4.5V <= VCC < 5.5V (Note 1) 4
Data output disable time TCZ 200 ns 1.8V <= VCC < 4.5V (Note 1) 4
Status valid time TSV 200 ns 4.5V <= VCC < 5.5V, CL = 100 pF 4
Status valid time TSV 300 ns 2.5V <= VCC < 4.5V, CL = 100 pF 4
Program cycle time TWC 6 ms Erase/Write mode (AA and LC versions) 4
ERAL mode time TEC 6 ms ERAL mode, 4.5V <= VCC <= 5.5V 4
WRAL mode time TWL 15 ms WRAL mode, 4.5V <= VCC <= 5.5V 4
Supply voltage (device VCC range) VCC 2.5 5.5 V 93LC56B, device selection table 1
Operating ambient temperature, Industrial (I) TA -40 85 °C Industrial (I) grade 1
VCC supply voltage (absolute maximum) VCC 7 V 3
Voltage on all inputs and outputs w.r.t. VSS -0.6 V 3
Storage temperature -65 150 °C 3
Ambient temperature with power applied -40 125 °C 3

CAD (KiCad official)

  • Symbol: 93LC56B-I
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: PDIP-8 (KiCad packages3D, STEP)
  • 3D model files: 93lc56b-i-etched.step / 93lc56b-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 93lc56b-i.step / 93lc56b-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (35 pp, sha256 e4b504cfbbafeadd, retrieved 2026-10-14, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF